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| User's Manual PD78064, 78064Y Subseries 8-Bit Single-Chip Microcontrollers PD78062 PD78063 PD78064 PD78P064 PD78062Y PD78063Y PD78064Y PD78P064Y Document No. U10105EJ4V1UM00 (4th edition) Date Published November 1999 N CP(K) (c) Printed in Japan 1993 [MEMO] User's Manual U10105EJ4V1UM00 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP is a trademark of NEC Corporation. IEBus, QTOP are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. User's Manual U10105EJ4V1UM00 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: PD78P064KL-T, 78P064YKL-T The customer must judge the need for license: PD78062GC- x x x -7EA, 78062YGC- x x x -7EA, PD78062GF- x x x -3BA, 78062YGF- x x x -3BA, PD78063GC- x x x -7EA, 78063YGC- x x x -7EA, PD78063GF- x x x -3BA, 78063YGF- x x x -3BA, PD78064GC- x x x -7EA, 78064YGC- x x x -7EA, PD78064GF- x x x -3BA, 78064YGF- x x x -3BA, PD78P064GC-7EA, 78P064YGC-7EA, PD78P064GF-3BA, 78P064YGF-3BA User's Manual U10105EJ4V1UM00 The application circuits and their parameters are for references only and are not intended for use in actual designin's. Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7D 98.12 User's Manual U10105EJ4V1UM00 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 User's Manual U10105EJ4V1UM00 Major Revised Points (1/2) Page Throughout p.8 p.36 Revisions PD78064Y subseries has been added for target devices. Section 1.5 "78K/0 Series Expansion" has been modified. Table 3-1. "Pin Input/Output Circuit Types" has beem modified. * Recommended connections of the following unused pins P07/XT1, P110 to P117, VPP * Input/output circuit type of the following pins P110 to P117 PM2 given in Figure 6-17. "Port Mode Register Format" has been modified. A caution given in Figure 7-4. "Oscillation Mode Selection Register Format" has been modified and added. A caution given in Figure 7-6. "External Circuit of Main System Clock Oscillator" has been modified. Section 7.4.4 "When no subsystem clocks are used" has been modified. Connection of XT1 pin: Connect to VSS -> Connect to V DD. Figure 10-1. "Watch Timer Block Diagram" has been modified. Figure 14-2. "A/D Converter Mode Register Format" has been modified. Section 14.5(7) "AV DD pin" has been modified and Figure 14-12. "Handling of AVDD Pin" has been added. Figure 15-4. "Serial Operating Mode Register 0 Format" has been modified. Figure 15-18. "Acknowledge Signal" has been modified. Figure 15-21. "RELD and CMDD Operations (Slave)" has been modified. Section 15.4.4(c) "Interrupt timing specify register (SINT)" has been modified. Figure 15-34. "SCK0/P27 Pin Configuration" has been modified. Figure 17-1. "Serial Interface Channel 2 Block Diagram" has been modified. Range of baud rate transmit/receive clock generated by main systm clock has been changed. 75 bps to 38400 bps -> 75 bps to 76800 bps Table 20-1. "HALT Mode Operating Status" has been modified. Description of HALT mode operating status has been separated to those during main system clock execution and during sub-system clock execution. Cautions given in Section 20.2.2(1) "STOP Mode Set and Operating Status" have been modified. Table 20-3. "STOP Mode Operating Status" has been modified. Description of STOP mode operating status has been separated to those during main system clock execution and during sub-system clock execution. p.108 p.117 p.118 p.121 p.197 p.223 p.233 p.244 p.261 p.267 p.284 p.287 p.339 p.348 p.429 p.432 p.432 User's Manual U10105EJ4V1UM00 (2/2) Page p.448 Revisions Description of QTOP microcontroller has been added to Section 22.5 "Screening of OneTime PROM Versions". p.465, 475 HP9000 series 700 has been added for the host machine of development tools and embedded software. p.469 p.470 p.476 System simulator (SM78K0) has been added for development tools. Section A.4 "Operating System for IBM PC" has been added. OS(MX78K0) has been added for embedded software. The asterisks on page margins show revised points. User's Manual U10105EJ4V1UM00 PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the PD78064 and 78064Y subseries and design and develop its application systems and programs. q q PD78064 subseries : PD78062, 78063, 78064, 78P064 PD78064Y subseries : PD78062Y, 78063Y, 78064Y, 78P064Note Note Under development Purpose This manual is intended for users to understand the functions described in the Organization below. Organization The PD78064, 78064Y subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 series). PD78064, 78064Y subseries User's Manual q q q 78K/0 series User's Manual Instruction q q q Pin functions Internal block functions Interrupt Other on-chip peripheral functions CPU functions Instruction set Explanation of each instruction q How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. q When you want to understand the functions in general: Read this manual in the order of the contents. How to interpret the register format: For the circled bit number, the bit name is defined as a reserved word in RA78K/0, and in CC78K/0, already defined in the header file named sfrbit.h. q q When you know a register name and want to confirm its details: Read APPENDIX C REGISTER INDEX. To know the PD78064 and 78064Y subseries instruction function in detail: Refer to the 78K/0 series User's Manual: Instructions (IEU-1372) To know the electrical specifications of the PD78064 and 78064Y subseries: Refer to separately available Data Sheet PD78062, 78063 and 78064 (IC-3244), q q PD78P064 Data Sheet (IC-3224) PD78062Y, 78063Y, 78064Y Data Sheet (IC-3235) q To know the application example of each function of the PD78064 and 78064Y subseries: Refer to separately available Application Note 78K/0 Series: Basic (III) (In preparation), 78K/0 series Application Note: Floating-Point Operation Program (IEA1289) User's Manual U10105EJ4V1UM00 Chapter Organization: This manual divides the descriptions for the PD78064 and 78064Y subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter PD78064 Subseries Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Outline (PD78064 Subseries) Outline (PD78064Y Subseries) Pin Function (PD78064 Subseries) Pin Function (PD78064Y Subseries) CPU Architecture Port Functions Clock Generator 16-Bit Timer/Event Counter 8-Bit Timer/Event Counters 1 and 2 Watch Timer Watchdog Timer Clock Output Control Circuit Buzzer Output Control Circuit A/D Converter Serial Interface Channel 0 (PD78064 Subseries) Serial Interface Channel 0 (PD78064Y Subseries) Serial Interface Channel 2 LCD Controller / Driver Interrupt and Test Functions Standby Function Reset Function -- -- -- PD78064Y Subseries -- -- -- PD78P064, PD78P064Y Instruction Set User's Manual U10105EJ4V1UM00 Differences between PD78064 and PD78064Y subseries: The PD78064 and PD78064Y subseries are different in the following functions of the serial interface channel 0. Modes of serial interface channel 0 PD78064 Subseries PD78064Y Subseries -- 3-wire serial I/O mode 2-wire serial I/O mode SBI (serial bus interface) mode I C (Inter IC) bus mode : Supported 2 -- -- : Not supported Legend Data representation weight Active low representations Note Caution Remarks Numeral representations : : : : : : High digits on the left and low digits on the right xxx (line over the pin and signal names) Description of note in the text. Information requiring particular attention Additional explanatory material Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH User's Manual U10105EJ4V1UM00 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. q Related documents for PD78064 subseries Document name Document No. English Japanese U12338J U12589J U10105J U12326J U12696J U10182J U13482J PD78062, 78063, 78064 Data Sheet PD78P064 Data Sheet PD78064, 78064Y Subseries User's Manual 78K/0 Series User's Manual--Instruction U12338E U12589E This manual U12326E -- U10182E IEA-1289 PD78064, 78064B Subseries Special Function Register Table 78K/0 Series Application Note Basics III Floating-point operation program q Related documents for PD78064Y subseries Document name Document No. English Japanese U10337J U10321J U10105J U12326J IEM-5583 U10182J U13482J PD78062Y, 78063Y, 78064Y Data Sheet PD78P064Y Preliminary Product Information PD78064, 78064Y Subseries User's Manual 78K/0 Series User's Manual--Instruction U10337E IP-3236 This manual U12326E -- Basics III Floating-point operation program U10182E IEA-1289 PD78064Y Subseries Special Function Register Table 78K/0 Series Application Note Caution The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design. User's Manual U10105EJ4V1UM00 q Development Tool Documents (User's Manuals) Document Name Document No. English RA78K0 Assembler Package Operation Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS ) Base PG-1500 Controller IBM PC Series (PC DOS ) Base IE-78000-R IE-78000-R-BK IE-78064-R-EM EP-78064 SM78K0 System Simulator -- Windows based SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Guide Reference TM TM Japanese U11802J U11801J U11789J U12323J U11517J U11518J U11940J EEU-704 EEU-5008 U11376J EEU-867 EEU-905 EEU-934 U10181J U10092J U11802E U11801E U11789E EEU-1402 U11517E U11518E U11940E EEU-1291 U10540E U11376E EEU-1427 EEU-1443 EEU-1469 U10181E U10092E ID78K0-NS Integrated Debugger, Windows based ID78K0 Integrated Debugger, EWS based ID78K0 Integrated Debugger, Windows based ID78K0 Integrated Debugger, PC based -- -- U11649E U11539E U12900J U11151J U11649J U11539J Caution The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design. User's Manual U10105EJ4V1UM00 q Documents for Embedded Software (User's Manual) Document No. English Japanese U11537J U11536J U12257J Document Name 78K/0 Series Real-Time OS Fundamentals Installation U11537E U11536E U12257E 78K/0 Series OS MX78K0 Fundamental q Other Documents Document Name Document No. English Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Review of Quality and Reliability Handbook Guide to Microcomputer-Related Products by Third party X13769X C10535E C11531E C10983E C11892E -- -- C10535J C11531J C10983J C11892J C12769J U11416J Caution The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design. User's Manual U10105EJ4V1UM00 CONTENTS CHAPTER 1 OUTLINE (PD78064 Subseries) .............................................................................. 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Features ............................................................................................................................. Applications ...................................................................................................................... Ordering Information ...................................................................................................... Pin Configuration (Top View) ........................................................................................ 78K/0 Series Expansion .................................................................................................. Block Diagram .................................................................................................................. Outline of Function .......................................................................................................... Mask Options ................................................................................................................... 1 1 2 2 3 8 10 11 12 13 13 14 14 15 20 22 23 24 25 25 25 28 CHAPTER 2 OUTLINE (PD78064Y Subseries) ............................................................................ 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Features ............................................................................................................................. Applications ...................................................................................................................... Ordering Information ...................................................................................................... Pin Configuration (Top View) ........................................................................................ 78K/0 Series Expansion .................................................................................................. Block Diagram .................................................................................................................. Outline of Function .......................................................................................................... Mask Options ................................................................................................................... PIN FUNCTION (PD78064 Subseries) .................................................................. CHAPTER 3 3.1 Pin Function List .............................................................................................................. 3.1.1 3.1.2 Normal operating mode pins .............................................................................................. PROM programming mode pins (PD78P064 only) ......................................................... P00 to P05, P07 (Port 0) .................................................................................................... P10 to P17 (Port 1) ............................................................................................................. P25 to P27 (Port 2) ............................................................................................................. P30 to P37 (Port 3) ............................................................................................................. P70 to P72 (Port 7) ............................................................................................................. P80 - P87 (Port 8) .............................................................................................................. P90 - P97 (Port 9) .............................................................................................................. P100 - P103 (Port 10) ........................................................................................................ P110 - P117 (Port 11) ........................................................................................................ COM0 to COM3 ................................................................................................................. VLC0 - VLC2 ........................................................................................................................... BIAS ..................................................................................................................................... AVREF .................................................................................................................................... AVDD ..................................................................................................................................... AVSS ..................................................................................................................................... RESET .................................................................................................................................. 3.2 Description of Pin Functions .......................................................................................... 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12 3.2.13 3.2.14 3.2.15 3.2.16 29 29 30 30 31 32 33 33 33 33 34 34 34 34 34 34 34 User's Manual U10105EJ4V1UM00 3.2.17 3.2.18 3.2.19 3.2.20 3.2.21 3.2.22 X1 and X2 ............................................................................................................................ XT1 and XT2 ........................................................................................................................ VDD ....................................................................................................................................... VSS ....................................................................................................................................... VPP (PD78P064 only) ......................................................................................................... IC (Mask ROM version only) .............................................................................................. 34 34 35 35 35 35 3.3 Input/output Circuits and Recommended Connection of Unused Pins .................. 36 41 41 41 44 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) ................................................................. 4.1 Pin Function List .............................................................................................................. 4.1.1 4.1.2 Normal operating mode pins .............................................................................................. PROM programming mode pins (PD78P064Y only) ....................................................... P00 to P05, P07 (Port 0) .................................................................................................... P10 to P17 (Port 1) ............................................................................................................. P25 to P27 (Port 2) ............................................................................................................. P30 to P37 (Port 3) ............................................................................................................. P70 to P72 (Port 7) ............................................................................................................. P80 - P87 (Port 8) .............................................................................................................. P90 - P97 (Port 9) .............................................................................................................. P100 - P103 (Port 10) ........................................................................................................ P110 - P117 (Port 11) ........................................................................................................ COM0 to COM3 ................................................................................................................. VLC0 - VLC2 ........................................................................................................................... BIAS ..................................................................................................................................... AVREF .................................................................................................................................... AVDD ..................................................................................................................................... AVSS ..................................................................................................................................... RESET .................................................................................................................................. X1 and X2 ............................................................................................................................ XT1 and XT2 ........................................................................................................................ VDD ....................................................................................................................................... VSS ....................................................................................................................................... VPP (PD78P064Y only) ...................................................................................................... IC (Mask ROM version only) .............................................................................................. 4.2 Description of Pin Functions .......................................................................................... 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 4.2.16 4.2.17 4.2.18 4.2.19 4.2.20 4.2.21 4.2.22 45 45 46 46 47 48 49 49 49 49 50 50 50 50 50 50 50 50 50 51 51 51 51 4.3 Input/output Circuits and Recommended Connection of Unused Pins .................. 52 57 57 61 62 62 63 CHAPTER 5 CPU ARCHITECTURE ................................................................................................. 5.1 Memory Spaces ................................................................................................................ 5.1.1 5.1.2 5.1.3 5.1.4 Internal program memory space ........................................................................................ Internal data memory space .............................................................................................. Special Function Register (SFR) area ................................................................................ Data memory addressing ................................................................................................... Control registers ................................................................................................................. General registers ................................................................................................................ Special Function Register (SFR) ......................................................................................... User's Manual U10105EJ4V1UM00 5.2 Processor Registers ......................................................................................................... 5.2.1 5.2.2 5.2.3 67 67 69 71 5.3 Instruction Address Addressing ................................................................................... 5.3.1 5.3.2 5.3.3 5.3.4 Relative Addressing ............................................................................................................ Immediate addressing ........................................................................................................ Table indirect addressing ................................................................................................... Register addressing ............................................................................................................ Implied addressing .............................................................................................................. Register addressing ............................................................................................................ Direct addressing ................................................................................................................ Short direct addressing ...................................................................................................... Special-Function Register (SFR) addressing ...................................................................... Register indirect addressing .............................................................................................. Based addressing ............................................................................................................... Based indexed addressing ................................................................................................. Stack addressing ................................................................................................................. 75 75 76 77 78 5.4 Operand Address Addressing ........................................................................................ 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 79 79 80 81 82 84 85 86 87 87 CHAPTER 6 PORT FUNCTIONS ..................................................................................................... 6.1 6.2 Port Functions .................................................................................................................. Port Configuration ........................................................................................................... 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 Port 0 ................................................................................................................................... Port 1 ................................................................................................................................... Port 2 (PD78064 Subseries) ............................................................................................. Port 2 (PD78064Y Subseries) .......................................................................................... Port 3 ................................................................................................................................... Port 7 ................................................................................................................................... Port 8 ................................................................................................................................... Port 9 ................................................................................................................................... Port 10 ................................................................................................................................. Port 11 ................................................................................................................................. 89 89 92 92 94 95 97 99 100 102 103 104 105 6.3 6.4 Port Function Control Registers .................................................................................... Port Function Operations ............................................................................................... 6.4.1 6.4.2 6.4.3 Writing to input/output port ............................................................................................... Reading from input/output port ......................................................................................... Operations on input/output port ........................................................................................ 106 111 111 111 111 CHAPTER 7 CLOCK GENERATOR ................................................................................................. 7.1 7.2 7.3 7.4 Clock Generator Functions ............................................................................................. Clock Generator Configuration ...................................................................................... Clock Generator Control Register ................................................................................. System Clock Oscillator .................................................................................................. 7.4.1 7.4.2 7.4.3 7.4.4 Main system clock oscillator .............................................................................................. Subsystem clock oscillator ................................................................................................. Scaler ................................................................................................................................... When no subsystem clocks are used ............................................................................... Main system clock operations ........................................................................................... Subsystem clock operations .............................................................................................. User's Manual U10105EJ4V1UM00 113 113 113 115 118 118 119 121 121 7.5 Clock Generator Operations ........................................................................................... 7.5.1 7.5.2 122 123 124 7.6 Changing System Clock and CPU Clock Settings....................................................... 7.6.1 7.6.2 Time required for switchover between system clock and CPU clock ............................. System clock and CPU clock switching procedure .......................................................... 125 125 126 CHAPTER 8 16-BIT TIMER/EVENT COUNTER ............................................................................. 8.1 8.2 8.3 8.4 16-Bit 16-Bit 16-Bit 16-Bit 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 127 129 131 135 144 144 146 149 150 157 159 161 Timer/Event Timer/Event Timer/Event Timer/Event Counter Counter Counter Counter Functions ......................................................................... Configuration .................................................................. Control Registers ........................................................... Operations....................................................................... Interval timer operations .................................................................................................... PWM output operations ..................................................................................................... PPG output operations ....................................................................................................... Pulse width measurement operations ............................................................................... External event counter operation ....................................................................................... Square-wave output operation ........................................................................................... One-shot pulse output operation ....................................................................................... 8.5 16-Bit Timer/Event Counter Operating Precautions .................................................. 165 169 169 169 172 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2............................................................. 9.1 8-Bit Timer/Event Counters 1 and 2 Functions ........................................................... 9.1.1 9.1.2 8-bit timer/event counter mode ......................................................................................... 16-bit timer/event counter mode ....................................................................................... 9.2 9.3 9.4 8-Bit Timer/Event Counters 1 and 2 Configurations .................................................. 8-Bit Timer/Event Counters 1 and 2 Control Registers ............................................. 8-Bit Timer/Event Counters 1 and 2 Operations ........................................................ 9.4.1 9.4.2 8-bit timer/event counter mode ......................................................................................... 16-bit timer/event counter mode ....................................................................................... 174 178 183 183 188 9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2 ....................................................... 192 195 195 196 196 200 200 200 CHAPTER 10 WATCH TIMER ......................................................................................................... 10.1 10.2 10.3 10.4 Watch Watch Watch Watch 10.4.1 10.4.2 Timer Timer Timer Timer Functions ................................................................................................... Configuration ............................................................................................ Control Registers ..................................................................................... Operations ................................................................................................. Watch timer operation ........................................................................................................ Interval timer operation ...................................................................................................... CHAPTER 11 WATCHDOG TIMER ................................................................................................. 11.1 11.2 11.3 11.4 Watchdog Watchdog Watchdog Watchdog 11.4.1 11.4.2 201 201 203 204 207 207 208 Timer Timer Timer Timer Functions ............................................................................................ Configuration ..................................................................................... Control Registers ............................................................................... Operations .......................................................................................... Watchdog timer operation ................................................................................................. Interval timer operation ...................................................................................................... User's Manual U10105EJ4V1UM00 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT .................................................................... 12.1 Clock Output Control Circuit Functions ....................................................................... 12.2 Clock Output Control Circuit Configuration ................................................................ 12.3 Clock Output Function Control Registers .................................................................... CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT .................................................................. 13.1 Buzzer Output Control Circuit Functions ..................................................................... 13.2 Buzzer Output Control Circuit Configuration .............................................................. 13.3 Buzzer Output Function Control Registers .................................................................. CHAPTER 14 A/D CONVERTER ..................................................................................................... 14.1 14.2 14.3 14.4 A/D A/D A/D A/D Converter Converter Converter Converter Functions ................................................................................................ Configuration ......................................................................................... Control Registers .................................................................................. Operations .............................................................................................. 209 209 210 211 215 215 215 216 219 219 219 222 226 226 228 229 14.4.1 14.4.2 14.4.3 Basic operations of A/D converter ..................................................................................... Input voltage and conversion results ................................................................................. A/D converter operating mode ........................................................................................... 14.5 A/D Converter Cautions .................................................................................................. CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) .................................... 15.1 15.2 15.3 15.4 Serial Serial Serial Serial 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 231 235 236 238 242 249 249 250 255 281 287 Interface Interface Interface Interface Channel Channel Channel Channel 0 0 0 0 Functions ............................................................................ Configuration ..................................................................... Control Registers .............................................................. Operations .......................................................................... Operation stop mode .......................................................................................................... 3-wire serial I/O mode operation ....................................................................................... SBI mode operation ............................................................................................................ 2-wire serial I/O mode operation ....................................................................................... SCK0/P27 pin output manipulation .................................................................................... CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) ................................. 16.1 16.2 16.3 16.4 Serial Serial Serial Serial 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 289 290 292 296 303 303 304 308 314 331 334 Interface Interface Interface Interface Channel Channel Channel Channel 0 0 0 0 Functions ............................................................................ Configuration ..................................................................... Control Registers .............................................................. Operations .......................................................................... Operation stop mode .......................................................................................................... 3-wire serial I/O mode operation ....................................................................................... 2-wire serial I/O mode operation ....................................................................................... I2C bus mode operation ..................................................................................................... Cautions on use of I2 C bus mode ..................................................................................... SCK0/SCL/P27 pin output manipulation ............................................................................ User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 ........................................................................... 17.1 17.2 17.3 17.4 Serial Serial Serial Serial 17.4.1 17.4.2 17.4.3 337 337 338 342 350 350 352 365 Interface Interface Interface Interface Channel Channel Channel Channel 2 2 2 2 Functions ............................................................................ Configuration ..................................................................... Control Registers .............................................................. Operation ............................................................................ Operation stop mode .......................................................................................................... Asynchronous serial interface (UART) mode .................................................................... 3-wire serial I/O mode ........................................................................................................ CHAPTER 18 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 LCD CONTROLLER/DRIVER ................................................................................. 371 371 372 374 377 378 379 383 387 387 390 393 397 LCD Controller/Driver Functions ................................................................................... LCD Controller/Driver Configuration ............................................................................ LCD Controller/Driver Control Registers ...................................................................... LCD Controller/Driver Settings ...................................................................................... LCD Display Data Memory ............................................................................................. Common Signals and Segment Signals ....................................................................... Supply of LCD Drive Voltages VLC0, VLC1, VLC2 ........................................................................ Display Modes .................................................................................................................. 18.8.1 18.8.2 18.8.3 18.8.4 Static Display Example ....................................................................................................... 2-Time-Division Display Example ....................................................................................... 3-Time-Division Display Example ....................................................................................... 4-Time-Division Display Example ....................................................................................... CHAPTER 19 INTERRUPT AND TEST FUNCTIONS .................................................................... 19.1 19.2 19.3 19.4 Interrupt Interrupt Interrupt Interrupt 19.4.1 19.4.2 19.4.3 19.4.4 19.4.5 19.5.1 19.5.2 401 401 402 405 414 414 417 420 420 422 Function Types ................................................................................................ Sources and Configuration ............................................................................ Function Control Registers ............................................................................ Servicing Operations ...................................................................................... Non-maskable interrupt acknowledge operation ............................................................... Maskable interrupt acknowledge operation ...................................................................... Software interrupt acknowledge operation ....................................................................... Multiple interrupt servicing ................................................................................................ Interrupt reserve ................................................................................................................. Registers controlling the test function .............................................................................. Test input signal acknowledge operation .......................................................................... 19.5 Test Functions .................................................................................................................. 423 423 426 CHAPTER 20 STANDBY FUNCTION ............................................................................................ 427 427 427 428 20.1 Standby Function and Configuration ........................................................................... 20.1.1 20.1.2 20.2.1 20.2.2 Standby function ................................................................................................................. Standby function control register ...................................................................................... HALT mode ......................................................................................................................... STOP mode ......................................................................................................................... 20.2 Standby Function Operations ........................................................................................ 429 429 432 User's Manual U10105EJ4V1UM00 CHAPTER 21 RESET FUNCTION .................................................................................................... 21.1 Reset Function.................................................................................................................. CHAPTER 22 PD78P064, 78P064Y ............................................................................................... 22.1 Memory Size Switching Register .................................................................................. 22.2 PROM Programming ........................................................................................................ 22.2.1 22.2.2 22.2.3 Operating modes ................................................................................................................ PROM write procedure ...................................................................................................... PROM reading procedure ................................................................................................... 435 435 439 440 441 441 443 447 22.3 Erasure Procedure (PD78P064KL-T and 78P064YKL-T Only) ................................... 22.4 Opaque Film Masking the Window (PD78P064KL-T and 78P064YKL-T Only) ...... 22.5 Screening of One-Time PROM Versions ...................................................................... CHAPTER 23 INSTRUCTION SET .................................................................................................. 23.1 Legends Used in Operation List .................................................................................... 23.1.1 23.1.2 23.1.3 Operand identifiers and description methods ................................................................... Description of "operation" column ................................................................................... Description of "flag operation" column ............................................................................ 448 448 448 449 450 450 451 451 23.2 Operation List ................................................................................................................... 23.3 Instructions Listed by Addressing Type ....................................................................... 452 460 User's Manual U10105EJ4V1UM00 APPENDIX A DEVELOPMENT TOOLS .......................................................................................... A.1 A.2 A.3 Language Processing Software ..................................................................................... PROM Programming Tools ............................................................................................. Debugging Tool ................................................................................................................ A.3.1 A.3.2 Hardware ............................................................................................................................. Software .............................................................................................................................. 465 466 467 468 468 469 A.4 Operating Systems for IBM PC ...................................................................................... 470 475 475 477 479 479 482 485 APPENDIX B EMBEDDED SOFTWARE ......................................................................................... B.1 B.2 Real-time OS ..................................................................................................................... Fuzzy Inference Development Support System .......................................................... REGISTER INDEX .................................................................................................... APPENDIX C C.1 C.2 Register Name Index ....................................................................................................... Register Symbol Index .................................................................................................... REVISION HISTORY ............................................................................................... APPENDIX D User's Manual U10105EJ4V1UM00 LIST OF FIGURES (1/8) Figure No. 3-1 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 Title Pin Input/Output Circuit of List ............................................................................................ Pin Input/Output Circuit of List ............................................................................................ Memory Map (PD78062, 78062Y) ..................................................................................... Memory Map (PD78063, 78063Y) ..................................................................................... Memory Map (PD78064, 78064Y) ..................................................................................... Memory Map (PD78P064, 78P064Y) ................................................................................. Data Memory Addressing (PD78062, 78062Y) ................................................................. Data Memory Addressing (PD78063, 78063Y) ................................................................. Data Memory Addressing (PD78064, 78064Y) ................................................................. Data Memory Addressing (PD78P064, 78P064Y) ............................................................. Program Counter Configuration ........................................................................................... Program Status Word Configuration .................................................................................... Stack Pointer Configuration .................................................................................................. Data to be Saved to Stack Memory .................................................................................... Data to be Reset from Stack Memory ................................................................................ General Register Configuration ............................................................................................ Port Types ............................................................................................................................. P00 and P07 Configurations ................................................................................................. P01 to P05 Configurations ................................................................................................... P10 to P17 Configurations ................................................................................................... P25, P26 Configurations (PD78064 subseries) ................................................................. P27 Configuration (PD78064 subseries) ............................................................................ P25, P26 Configurations (PD78064Y subseries) ............................................................... P27 Configuration (PD78064Y subseries) ......................................................................... P30 to P37 Configurations ................................................................................................... P70 Configuration ................................................................................................................. P71 and P72 Configurations ................................................................................................. P80 to P87 Configurations ................................................................................................... P90 to P97 Configurations ................................................................................................... P100 to P103 Configurations ............................................................................................... P110 to P117 Configurations ............................................................................................... Block Diagram of Falling Edge Detection Circuit ................................................................ Port Mode Register Format ................................................................................................. Pull-Up Resistor Option Register Format ............................................................................ Key Return Mode Register Format ...................................................................................... Page 38 54 57 58 59 60 63 64 65 66 67 67 68 68 69 70 89 93 93 94 95 96 97 98 99 100 101 102 103 104 105 105 108 109 110 User's Manual U10105EJ4V1UM00 LIST OF FIGURES (2/8) Figure No. Title Page 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 Block Diagram of Clock Generator ...................................................................................... Subsystem Clock Feedback Resistor .................................................................................. Processor Clock Control Register Format ........................................................................... Oscillation Mode Selection Register Format ....................................................................... Main System Clock Waveform due to Writing to OSMS ................................................... External Circuit of Main System Clock Oscillator ............................................................... External Circuit of Subsystem Clock Oscillator ................................................................... Examples of Oscillator with Bad Connection ...................................................................... Main System Clock Stop Function ...................................................................................... System Clock and CPU Clock Switching ............................................................................. 16-Bit Timer/Event Counter Block Diagram ........................................................................ 16-Bit Timer/Event Counter Output Control Circuit Block Diagram ................................... Timer Clock Selection Register 0 Format ............................................................................ 16-Bit Timer Mode Control Register Format ....................................................................... Capture/Compare Control Register 0 Format ...................................................................... 16-Bit Timer Output Control Register Format ..................................................................... Port Mode Register 3 Format .............................................................................................. External Interrupt Mode Register 0 Format ........................................................................ Sampling Clock Select Register Format .............................................................................. Control Register Settings for Interval Timer Operation ...................................................... Interval Timer Configuration Diagram .................................................................................. Interval Timer Operation Timings ........................................................................................ Control Register Settings for PWM Output Operation ....................................................... Example of D/A Converter Configuration with PWM Output ............................................ TV Tuner Application Circuit Example ................................................................................. Control Register Settings for PPG Output Operation ......................................................... Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register .............................................................. Configuration Diagram for Pulse Width Measurement by Free-Running Counter ............ Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) .................................................... Control Register Settings for Two Pulse Width Measurements with Free-Running Counter .................................................................................................. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) ............................................................................................... Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers .................................................................................................. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) ................................... Control Register Settings for Pulse Width Measurement by Means of Restart .............. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) ............................................................................................... 114 115 116 117 117 118 119 119 123 126 132 133 136 138 139 140 141 142 143 144 145 145 147 148 148 149 150 151 151 152 153 154 155 156 156 User's Manual U10105EJ4V1UM00 LIST OF FIGURES (3/8) Figure No. Title Page 8-26 8-27 8-28 8-29 8-30 8-31 8-32 8-33 8-34 8-35 8-36 8-37 8-38 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 10-1 10-2 10-3 11-1 11-2 11-3 Control Register Settings in External Event Counter Mode ............................................... External Event Counter Configuration Diagram .................................................................. External Event Counter Operation Timings (with Rising Edge Specified) ......................... Control Register Settings in Square-Wave Output Mode .................................................. Square-Wave Output Operation Timing .............................................................................. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ................................................................................................................... Timing of One-Shot Pulse Output Operation Using Software Trigger .............................. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger .......................................................................................................... Timing of One-Shot Pulse Output Operation Using External Trigger (With Rising Edge Specified) ................................................................................................ 16-Bit Timer Register Start Timing ...................................................................................... Timings After Change of Compare Register During Timer Count Operation .................... Capture Register Data Retention Timing ............................................................................. Operation Timing of OVF0 Flag ........................................................................................... 8-Bit Timer/Event Counters 1 and 2 Block Diagram ........................................................... Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 ............................. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 ............................. Timer Clock Select Register 1 Format ................................................................................ 8-Bit Timer Mode Control Register Format ......................................................................... 8-Bit Timer Output Control Register Format ....................................................................... Port Mode Register 3 Format .............................................................................................. Interval Timer Operation Timings ........................................................................................ External Event Counter Operation Timings (with Rising Edge Specified) ......................... Interval Timer Operation Timing .......................................................................................... External Event Counter Operation Timings (with Rising Edge Specified) ......................... 8-Bit Timer Registers 1 and 2 Start Timing ......................................................................... External Event Counter Operation Timing ........................................................................... Timing after Compare Register Change during Timer Count Operation ........................... Watch Timer Block Diagram ................................................................................................ Timer Clock Select Register 2 Format ................................................................................ Watch Timer Mode Control Register Format ...................................................................... Watchdog Timer Block Diagram .......................................................................................... Timer Clock Select Register 2 Format ................................................................................ Watchdog Timer Mode Register Format ............................................................................. 157 158 158 159 160 161 162 163 164 165 165 166 167 175 176 176 179 180 181 182 183 186 188 190 192 192 193 197 198 199 203 205 206 User's Manual U10105EJ4V1UM00 LIST OF FIGURES (4/8) Figure No. Title Page 12-1 12-2 12-3 12-4 13-1 13-2 13-3 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 Remote Controlled Output Application Example ................................................................ Clock Output Control Circuit Block Diagram ....................................................................... Timer Clock Select Register 0 Format ................................................................................ Port Mode Register 3 Format .............................................................................................. Buzzer Output Control Circuit Block Diagram ..................................................................... Timer Clock Select Register 2 Format ................................................................................ Port Mode Register 3 Format .............................................................................................. A/D Converter Block Diagram .............................................................................................. A/D Converter Mode Register Format ................................................................................. A/D Converter Input Select Register Format ...................................................................... External Interrupt Mode Register 1 Format ........................................................................ A/D Converter Basic Operation ............................................................................................ Relations between Analog Input Voltage and A/D Conversion Result .............................. A/D Conversion by Hardware Start ...................................................................................... A/D Conversion by Software Start ....................................................................................... Example of Method of Reducing Current Consumption in Standby Mode ....................... Analog Input Pin Disposition ................................................................................................ A/D Conversion End Interrupt Generation Timing .............................................................. Handling of AVDD Pin ............................................................................................................ Serial Bus Interface (SBI) System Configuration Example ................................................. Serial Interface Channel 0 Block Diagram ............................................................................. Timer Clock Select Register 3 Format ................................................................................... Serial Operating Mode Register 0 Format ............................................................................. Serial Bus Interface Control Register Format ........................................................................ Interrupt Timing Specify Register Format ............................................................................. 3-Wire Serial I/O Mode Timings ............................................................................................ RELT and CMDT Operations ................................................................................................. Circuit of Switching in Transfer Bit Order .............................................................................. Example of Serial Bus Configuration with SBI ...................................................................... SBI Transfer Timings ............................................................................................................. Bus Release Signal ................................................................................................................ Command Signal ................................................................................................................... Addresses ............................................................................................................................. Slave Selection with Address ................................................................................................ Commands ............................................................................................................................ Data ....................................................................................................................................... Acknowledge Signal .............................................................................................................. BUSY and READY Signals ..................................................................................................... RELT, CMDT, RELD, and CMDD Operations (Master) ......................................................... 209 210 212 213 215 217 218 220 223 224 225 227 228 229 230 231 232 233 233 237 239 243 244 246 248 253 253 254 255 257 258 258 259 259 260 260 261 262 267 User's Manual U10105EJ4V1UM00 LIST OF FIGURES (5/8) Figure No. Title Page 15-21 15-22 15-23 15-24 15-25 15-26 15-27 15-28 15-29 15-30 15-31 15-32 15-33 15-34 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 16-20 16-21 16-22 16-23 16-24 16-25 RELD and CMDD Operations (Slave) .................................................................................... ACKT Operation ..................................................................................................................... ACKE Operations ................................................................................................................... ACKD Operations .................................................................................................................. BSYE Operation ..................................................................................................................... Pin Configuration ................................................................................................................... Address Transmission from Master Device to Slave Device (WUP = 1) .............................. Command Transmission from Master Device to Slave Device ............................................. Data Transmission from Master Device to Slave Device ...................................................... Data Transmission from Slave Device to Master Device ...................................................... Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ......................................... 2-Wire Serial I/O Mode Timings ............................................................................................ RELT and CMDT Operations ................................................................................................. SCK0/P27 Pin Configuration .................................................................................................. Serial Bus Configuration Example Using I2C Bus .................................................................. Serial Interface Channel 0 Block Diagram ............................................................................. Timer Clock Select Register 3 Format ................................................................................... Serial Operating Mode Register 0 Format ............................................................................. Serial Bus Interface Control Register Format ........................................................................ Interrupt Timing Specify Register Format ............................................................................. 3-Wire Serial I/O Mode Timings ............................................................................................ RELT and CMDT Operations ................................................................................................. Circuit of Switching in Transfer Bit Order .............................................................................. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ......................................... 2-Wire Serial I/O Mode Timings ............................................................................................ RELT and CMDT Operations ................................................................................................. Example of Serial Bus Configuration Using I C Bus .............................................................. I2C Bus Serial Data Transfer Timing ...................................................................................... Start Condition ....................................................................................................................... Address ................................................................................................................................. Transfer Direction Specification ............................................................................................ Acknowledge Signal .............................................................................................................. Stop Condition ....................................................................................................................... Wait Signal ............................................................................................................................ Pin Configuration ................................................................................................................... Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) .................................................................... Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) .................................................................... Start Condition Output .......................................................................................................... Slave Wait Release (Transmission) ....................................................................................... 2 267 268 269 270 270 273 275 276 277 278 281 285 286 287 291 293 297 298 299 301 306 306 307 308 312 313 314 315 316 316 316 317 317 318 323 325 328 331 332 User's Manual U10105EJ4V1UM00 LIST OF FIGURES (6/8) Figure No. Title Page 16-26 16-27 16-28 16-29 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 18-19 18-20 18-21 18-22 18-23 Slave Wait Release (Reception) ............................................................................................ SCK0/SCL/P27 Pin Configuration .......................................................................................... SCK0/SCL/P27 Pin Configuration .......................................................................................... Logic Circuit of SCL Signal .................................................................................................... Serial Interface Channel 2 Block Diagram ............................................................................. Baud Rate Generator Block Diagram ..................................................................................... Serial Operating Mode Register 2 Format ............................................................................. Asynchronous Serial Interface Mode Register Format ......................................................... Asynchronous Serial Interface Status Register Format ......................................................... Baud Rate Generator Control Register Format ..................................................................... Asynchronous Serial Interface Transmit/Receive Data Format ............................................. Asynchronous Serial Interface Transmission Completion Interrupt Timing .......................... Asynchronous Serial Interface Reception Completion Interrupt Timing ............................... Receive Error Timing ............................................................................................................. 3-Wire Serial I/O Mode Timing .............................................................................................. LCD Controller/Driver Block Diagram .................................................................................... LCD Clock Select Circuit Block Diagram ............................................................................... LCD Display Mode Register Format ...................................................................................... LCD Display Control Register Format ................................................................................... Relationship between LCD Display Data Memory Contents and Segment/Common Outputs .................................................................................................. Common Signal Waveform ................................................................................................... Common Signal and Static Signal Voltages and Phases ....................................................... LCD Drive Power Supply Connection Examples (with On-Chip Split Resistor) ..................... LCD Drive Power Supply Connection Examples (with External Split Resistor) ..................... Example of LCD Drive Voltage Supply from Off-Chip ........................................................... Static LCD Display Pattern and Electrode Connections ........................................................ Static LCD Panel Connection Example .................................................................................. Static LCD Drive Waveform Examples .................................................................................. 2-Time-Division LCD Display Pattern and Electrode Connections ......................................... 2-Time-Division LCD Panel Connection Example .................................................................. 2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) .................................... 3-Time-Division LCD Display Pattern and Electrode Connections ......................................... 3-Time-Division LCD Panel Connection Example .................................................................. 3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) .................................... 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ..................................... 4-Time-Division LCD Display Pattern and Electrode Connections ......................................... 4-Time-Division LCD Panel Connection Example .................................................................. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) .................................... 333 334 335 335 339 340 342 343 345 346 359 361 362 363 370 372 373 374 376 378 381 382 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 User's Manual U10105EJ4V1UM00 LIST OF FIGURES (7/8) Figure No. Title Page 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 19-18 19-19 19-20 19-21 20-1 20-2 20-3 20-4 20-5 21-1 21-2 21-3 21-4 22-1 22-2 22-3 22-4 22-5 22-6 Basic Configuration of Interrupt Function .............................................................................. Interrupt Request Flag Register Format ................................................................................ Interrupt Mask Flag Register Format .................................................................................... Priority Specify Flag Register Format .................................................................................... External Interrupt Mode Register 0 Format .......................................................................... External Interrupt Mode Register 1 Format .......................................................................... Sampling Clock Select Register Format ................................................................................ Noise Remover Input/Output Timing (during rising edge detection) ..................................... Program Status Word Format ............................................................................................... Non-Maskable Interrupt Acknowledge Flowchart ................................................................. Non-Maskable Interrupt Acknowledge Timing ...................................................................... Non-Maskable Interrupt Request Acknowledge Operation ................................................... Interrupt Acknowledge Processing Algorithm ....................................................................... Interrupt Acknowledge Timing (Minimum Time) ................................................................... Interrupt Acknowledge Timing (Maximum Time) .................................................................. Multiple Interrupt Example .................................................................................................... Interrupt Request Hold .......................................................................................................... Basic Configuration of Test Function .................................................................................... Format of Interrupt Request Flag Register 1L ....................................................................... Format of Interrupt Mask Flag Register 1L ........................................................................... Key Return Mode Register Format ....................................................................................... Oscillation Stabilization Time Select Register Format ........................................................... HALT Mode Clear upon Interrupt Generation ....................................................................... HALT Mode Release by RESET Input ................................................................................... STOP Mode Release by Interrupt Generation ....................................................................... Release by STOP Mode RESET Input ................................................................................... Block Diagram of Reset Function .......................................................................................... Timing of Reset Input by RESET Input .................................................................................. Timing of Reset due to Watchdog Timer Overflow .............................................................. Timing of Reset Input in STOP Mode by RESET Input ......................................................... Memory Size Switching Register Format .............................................................................. Page Program Mode Flowchart ............................................................................................. Page Program Mode Timing .................................................................................................. Byte Program Mode Flowchart ............................................................................................. Byte Program Mode Timing .................................................................................................. PROM Read Timing ............................................................................................................... 403 406 407 408 409 410 411 412 413 415 415 416 418 419 419 421 422 423 424 424 425 428 430 431 433 434 435 436 436 436 440 443 444 445 446 447 User's Manual U10105EJ4V1UM00 LIST OF FIGURES (8/8) Figure No. Title Page A-1 A-2 A-3 A-4 Development Tool Configuration ........................................................................................... TGC-100SDW Drawing (For Reference Only) (Unit: mm) ..................................................... EV-9200GF-100 Drawing (For Reference Only) ..................................................................... EV-9200GF-100 Footprint (For Reference Only) .................................................................... 465 472 473 474 User's Manual U10105EJ4V1UM00 LIST OF TABLES (1/3) Table No. 1-1 2-1 3-1 4-1 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 Title Mask Options of Mask ROM Versions .................................................................................. Mask Options of Mask ROM Versions .................................................................................. Pin Input/Output Circuit Types .............................................................................................. Pin Input/Output Circuit Types .............................................................................................. Internal ROM Capacity .......................................................................................................... Vector Table .......................................................................................................................... Internal High-Speed RAM Capacity ....................................................................................... Special-Function Register List ............................................................................................... Port Functions (PD78064 subseries) ................................................................................... Port Functions (PD78064Y subseries) ................................................................................. Port Configuration ................................................................................................................. Port Mode Register and Output Latch Settings when Using Dual-Functions ....................... Clock Generator Configuration .............................................................................................. Maximum Time Required for CPU Clock Switchover ........................................................... Timer/Event Counter Types and Functions ........................................................................... 16-Bit Timer/Event Counter Interval Times ........................................................................... 16-Bit Timer/Event Counter Square-Wave Output Ranges ................................................... 16-Bit Timer/Event Counter Configuration ............................................................................ INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge ......................................... 16-Bit Timer/Event Counter Interval Times ........................................................................... 16-Bit Timer/Event Count Square-Wave Output Ranges ...................................................... 8-Bit Timer/Event Counters 1 and 2 Interval Times ............................................................... 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges ....................................... Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters ................................................................................... Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters ............................................................................. 8-Bit Timer/Event Counters 1 and 2 Configurations .............................................................. 8-Bit Timer/Event Counter 1 Interval Time ............................................................................ 8-Bit Timer/Event Counter 2 Interval Time ............................................................................ 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges ....................................... Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ..................................................... Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ..................................................... Page 12 24 36 52 61 61 62 73 90 91 92 107 113 125 128 129 130 131 134 146 160 170 171 172 173 174 184 185 187 189 191 User's Manual U10105EJ4V1UM00 LIST OF TABLES (2/3) Table No. Title Page 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 12-1 13-1 14-1 15-1 15-2 15-3 16-1 16-2 16-3 16-4 17-1 17-2 17-3 17-4 17-5 17-6 17-7 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 Interval Timer Interval Time ................................................................................................... Watch Timer Configuration ................................................................................................... Interval Timer Interval Time ................................................................................................... Watchdog Timer Inadvertent Program Overrun Detection Times ......................................... Interval Times ........................................................................................................................ Watchdog Timer Configuration ............................................................................................. Watchdog Timer Overrun Detection Time ............................................................................ Interval Timer Interval Time ................................................................................................... Clock Output Control Circuit Configuration ........................................................................... Buzzer Output Control Circuit Configuration ......................................................................... A/D Converter Configuration ................................................................................................. Differences between Channels 0 and 2 ................................................................................ Serial Interface Channel 0 Configuration ............................................................................... Various Signals in SBI Mode ................................................................................................. Differences between Channels 0 and 2 ................................................................................ Serial Interface Channel 0 Configuration ............................................................................... Serial Interface Channel 0 Interrupt Request Signal Generation ........................................... Signals in I2C Bus Mode ........................................................................................................ Serial Interface Channel 2 Configuration ............................................................................... Serial Interface Channel 2 Operating Mode Settings ............................................................ Relation between Main System Clock and Baud Rate .......................................................... Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) .. Relation between Main System Clock and Baud Rate .......................................................... Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) .. Receive Error Causes ............................................................................................................ Maximum Number of Display Pixels ..................................................................................... LCD Controller/Driver Configuration ...................................................................................... Frame Frequencies (Hz) ........................................................................................................ COM Signals ......................................................................................................................... LCD Drive Voltages ............................................................................................................... LCD Drive Voltages (with On-Chip Split Resistor) ................................................................. Selection and Non-Selection Voltages (COM0) ..................................................................... Selection and Non-Selection Voltages (COM0, COM1) ........................................................ Selection and Non-Selection Voltages (COM0 to COM2) ..................................................... Selection and Non-Selection Voltages (COM0 to COM3) ..................................................... 195 196 200 201 202 203 207 208 210 215 219 235 238 271 289 292 295 322 338 344 348 349 357 358 363 371 372 375 379 380 383 387 390 393 397 User's Manual U10105EJ4V1UM00 LIST OF TABLES (3/3) Table No. Title Page 19-1 19-2 19-3 19-4 19-5 19-6 20-1 20-2 20-3 20-4 21-1 22-1 22-2 22-3 23-1 Interrupt Source List .............................................................................................................. Various Flags Corresponding to Interrupt Request Sources ................................................. Times from Maskable Interrupt Request Generation to Interrupt Service ............................ Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ......................... Test Input Factors ................................................................................................................. Flags Corresponding to Test Input Signals ............................................................................ HALT Mode Operating Status ............................................................................................... Operation after HALT Mode Release .................................................................................... STOP Mode Operating Status ............................................................................................... Operation after STOP Mode Release .................................................................................... Hardware Status after Reset ................................................................................................. Differences among PD78P064, 78P064Y and Mask ROM Versions .................................. Examples of Memory Size Switching Register Settings ....................................................... PROM Programming Operating Modes ................................................................................ Operand Identifiers and Description Methods ...................................................................... 402 405 417 420 423 423 429 431 432 434 437 439 440 441 450 User's Manual U10105EJ4V1UM00 [MEMO] User's Manual U10105EJ4V1UM00 CHAPTER 1 OUTLINE (PD78064 Subseries) 1.1 Features q On-chip high-capacity ROM and RAM Type Part Number Program Memory (ROM) 16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes (Note) 1024 bytes (Note) Data Memory Internal High-Speed RAM 512 bytes 1024 bytes LCD RAM 40 x 4 bytes PD78062 PD78063 PD78064 PD78P064 Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register. q Instruction execution time changeable from high speed (0.4 s: In main system clock 5.0 MHz operation) to ultralow speed (122 s: In subsystem clock 32.768 kHz operation) q Instruction set suited to system control * Bit manipulation possible in all address spaces * Multiply and divide instructions q Fifty-seven I/O ports (including alternative function pins for segment signal output) q LCD Controller / Driver * Segment signal output: * Common signal output: * Bias: * Power supply voltage: Max. 40 Max. 4 VDD = 2.0 to 6.0 V (Static display mode) VDD = 2.5 to 6.0 V (1/3 bias method) VDD = 2.7 to 6.0 V (1/2 bias method) q 8-bit resolution A/D converter: 8 channels q Serial interface: 2 channels * 3-wire/SBI/2-wire mode: 1 channel * 3-wire/UART mode: 1 channel q Timer: 5 channels * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel q Twenty vectored interrupts q Two test inputs q Two types of on-chip clock oscillators (main system clock and subsystem clock) q Power supply voltage: VDD = 2.0 to 6.0 V 1/2, 1/3 bias switching possible User's Manual U10105EJ4V1UM00 1 CHAPTER 1 OUTLINE (PD78064 Subseries) 1.2 Applications Cellular phones, CD players, cameras, etc. 1.3 Ordering Information Part number Package 100-pin plastic QFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin ceramic WQFN Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One-time PROM One-time PROM EPROM PD78062GC-xxx-7EA PD78062GF-xxx-3BA PD78063GC-xxx-7EA PD78063GF-xxx-3BA PD78064GC-xxx-7EA PD78064GF-xxx-3BA PD78P064GC-7EA PD78P064GF-3BA PD78P064KL-T* * : Under development xxx indicates ROM code suffix. Remark 2 User's Manual U10105EJ4V1UM00 CHAPTER 1 OUTLINE (PD78064 Subseries) 1.4 Pin Configuration (Top View) (1) Normal operating mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm) PD78062GC-xxx-7EA, 78063GC-xxx-7EA, 78064GC-xxx-7EA, 78P064GC-7EA P10/ANI0 AVSS P117 P116 P115 P114 P113 P112 P111 P110 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET XT2 XT1/P07 VDD X1 X2 IC (VPP) P72/SCK2/ASCK P71/SO2/TxD P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P100 P101 VSS P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 COM0 COM1 COM2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P70/SI2/RxD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19 Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly. 2. Connect AVDD pin to VDD. 3. Connect AVSS pin to VSS. Remark Pin connection in parentheses is intended for the PD78P064. COM3 BIAS VLC0 VLC1 VLC2 VSS S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 User's Manual U10105EJ4V1UM00 3 CHAPTER 1 OUTLINE (PD78064 Subseries) 100-pin plastic QFP (14 x 20 mm) PD78062GF-xxx-3BA, 78063GF-xxx-3BA, 78064GF-xxx-3BA, 78P064GF-3BA 100-pin ceramic WQFN PD78P064KL-T* P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 P26/SO0/SB1 P27/SCK0 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK IC (VPP) X2 X1 VDD XT1/P07 XT2 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P110 P111 P112 P113 P114 P115 P116 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 VSS VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0 * : Under development Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly. 2. Connect AVDD pin to VDD. 3. Connect AVSS pin to VSS. Remark Pin connection in parentheses is intended for the PD78P064. 4 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P100 P101 VSS P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 User's Manual U10105EJ4V1UM00 CHAPTER 1 OUTLINE (PD78064 Subseries) P00 to P05, P07 P10 to P17 P25 to P27 P30 to P37 P70 to P72 P80 to P87 P90 to P97 P100 to P103 P110 to P117 INTP0 to INTP5 TI00, TI01 TI1, TI2 TO0 to TO2 SB0, SB1 SI0 to SI2 SO0 to SO2 SCK0 to SCK2 RxD TxD : : : : : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 7 Port 8 Port 9 Port 10 Port 11 Interrupt from Peripherals Timer Input Timer Input Timer Output Serial Bus Serial Input Serial Output Serial Clock Receive Data Transmit Data ASCK PCL BUZ S0 to S39 COM0 to COM3 VLC0 to VLC2 BIAS X1, X2 XT1, XT2 RESET ANI0 to ANI7 AVDD AVSS AVREF VDD VPP VSS IC : : : : : : : : : : : : : : : : : : Asynchronous Serial Clock Programmable Clock Buzzer Clock Segment Output Common Output LCD Power Supply LCD Power Supply Bias Control Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Programming Power Supply Ground Internally Connected User's Manual U10105EJ4V1UM00 5 CHAPTER 1 OUTLINE (PD78064 Subseries) (2) PROM programming mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm) PD78P064GC-7EA PGM (L) A9 RESET Open (L) VDD (L) Open VPP (L) (L) (L) VDD VSS (L) VSS (L) D0 D1 D2 D3 D4 D5 D6 D7 (L) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CE OE (L) (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) Cautions 1. (L) 2. VSS 4. Open : Connect individually to VSS via a pull-down resistor. : Connect to the ground. : Do not connect anything. 3. RESET : Set to the low level. 6 User's Manual U10105EJ4V1UM00 (L) CHAPTER 1 OUTLINE (PD78064 Subseries) 100-pin plastic QFP (14 x 20 mm) PD78P064GF-3BA 100-pin ceramic WQFN PD78P064KL-T* (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) (L) VPP Open (L) VDD (L) Open RESET A9 (L) PGM (L) OE CE (L) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (L) VDD VSS VSS (L) * : Under development Cautions 1. (L) 2. VSS 4. Open A0 to A16 D0 to D7 CE OE PGM : Connect individually to VSS via a pull-down resistor. : Connect to the ground. : Do not connect anything. RESET VDD VPP VSS : Reset : Power Supply : Programming Power Supply : Ground 3. RESET : Set to the low level. : Address Bus : Data Bus : Chip Enable : Output Enable : Program (L) (L) D0 D1 D2 D3 D4 D5 D6 D7 User's Manual U10105EJ4V1UM00 7 CHAPTER 1 OUTLINE (PD78064 Subseries) * 1.5 78K/0 Series Expansion 78K/0 series products evolution is illustrated below. Part numbers in the boxes indicate subseries names. Mass-produced Under development Y subseries supports I2C bus specifications. Performs control. 100-pin 100-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin PD78078 PD78070A PD78054 PD78018F PD78014 PD780001 PD78002 PD78083 Drives VFD (FIPs TM ). 78K/0 series 100-pin 80-pin 64-pin PD780208 PD78044A PD78024 Drives LCDs. 100-pin PD78064 PD78064Y Subseries for driving LCDs, has UART. Enhances I/O, FIP C/D based on PD78044A : Max. 53 display outputs Adds 6-bit U/D counter based on PD78024 : Max. 34 display outputs Basic subseries for driving FIPs : Max. 26 display outputs PD78002Y PD78078Y PD78070AY PD78054Y PD78018FY PD78014Y Adds timers and enhances external interface based on PD78054. ROM-less version of PD78078. Adds UART and D/A and enhances I/Os based on PD78014. Adds A/D and 16-bit timer based on PD78002. Adds A/D based on PD78002. Basic subseries for control applications Operates at 1.8 V and has UART. . Operates at 1.8 V and enhances ROM/RAM size selection based on PD78014 Supports IEBus.TM 80-pin PD78098 Adds IEBus controller based on PD78054. 8 User's Manual U10105EJ4V1UM00 CHAPTER 1 OUTLINE (PD78064 Subseries) Major differences among these subseries are tabulated below. Function Subseries Control PD78078 PD78070A PD78054 PD78018F PD78014 PD780001 PD78002 PD78083 FIP drive PD780208 PD78024 LCD drive IEbus Support PD78098 32K-60K 2ch 1ch 1ch 1ch 8ch 2ch 3ch(UART:1ch) 69 2.7 V PD78064 ROM capacity 32K-60K -- 16K-60K 8K-48K 8K-32K 8K 8K-16K 32K-40K 2ch 1ch -- -- 1ch -- 1ch 1ch -- 8ch 8ch -- 1ch 1ch (UART:1ch) 2ch 39 53 33 74 68 54 2ch 1ch 1ch 1ch 8ch -- 2ch(UART:1ch) 57 2.0 V -- 1.8 V 2.7 V 2ch -- 2ch Timer 8-bit 16-bit Watch Watchdog 4ch 1ch 1ch 1ch 8-bit A/D 8ch 8-bit D/A 2ch 3ch(UART:1ch) 88 61 69 53 Serial Interface I/O VDD MIN 1.8 V 2.7 V 2.0 V 1.8 V 2.7 V -- -- -- External extension PD78044A 16K-40K 24K-32K 16K-32K User's Manual U10105EJ4V1UM00 9 CHAPTER 1 OUTLINE (PD78064 Subseries) 1.6 Block Diagram TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit Timer/ Event Counter P00 P01-P05 P07 P10-P17 Port 0 8-bit Timer/ Event Counter 1 Port 1 Port 2 8-bit Timer/ Event Counter 2 P25-P27 Port 3 Watchdog Timer Port 7 P30-P37 P70-P72 Watch Timer Port 8 P80-P87 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 Serial Interface 0 78K/0 CPU Core ROM Port 9 P90-P97 Port 10 Serial Interface 2 P100-P103 Port 11 P110-P117 S0-S23 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/P00INTP5/P05 A/D Converter RAM LCD Controller/ Driver S24/P97S31/P90 S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD RESET X1 X2 XT1/P07 XT2 Interrupt Control BUZ/P36 Buzzer Output System Control PCL/P35 Clock Output Control VDD VSS IC (VPP) Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the PD78P064. 10 User's Manual U10105EJ4V1UM00 CHAPTER 1 OUTLINE (PD78064 Subseries) 1.7 Outline of Function PD78062 PD78063 PD78064 PD78P064 Part Number Item Internal memory ROM Mask ROM 16 Kbytes 24 Kbytes 1024 bytes 32 Kbytes PROM 32 KbytesNote 1024 bytesNote Internal high-speed RAM LCD RAM General register Instruction With main system clock selected cycle With subsystem clock selected 512 bytes 40 x 4 bits 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0 MHz) 122 s (@ 32.768 kHz) * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulate (set, reset, test, and Boolean operation) * BCD adjust, etc. Instruction set I/O port (including alternative function pins for segment signal output) * Total * CMOS input * CMOS I/O : 57 :2 : 55 A/D converter LCD controller / driver 8-bit resolution x 8 channels * Segment signal output: Max. 40 * Common signal output: Max. 4 * Bias: 1/2, 1/3 bias switching possible Serial interface * 3-wire/SBI/2-wire mode selection possible : 1 channel * 3-wire mode / UART mode selection possible : 1 channel Timer * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter * Watch timer * Watchdog timer Timer output Clock output : 2 channels : 1 channel : 1 channel Three outputs: (14-bit PWM output enable: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock) 32.768 kHz (@ 32.768 kHz with subsystem clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock) Note The capacities of the internal PROM and the internal high-speed RAM can be changed using the memory size switching register. User's Manual U10105EJ4V1UM00 11 CHAPTER 1 OUTLINE (PD78064 Subseries) Part Number Item Maskable interrupt Vectored interrupt Non-maskable interrupt Software interrupt Test input PD78062 PD78063 PD78064 PD78P064 Internal: 12 External: 6 Internal: 1 Internal: 1 Internal: 1 External: 1 Power supply voltage Operating ambient temperature Package VDD = 2.0 to 6.0 V TA = -40 to +85 C * 100-pin plastic QFP (Fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFNNote (PD78P064 only) Note Under development * 1.8 Mask Options The mask ROM versions (PD78062, 78063, 78064) provide split resistor mask options. By specifying this mask options at the time of ordering, split registers which enable to generate LCD drive voltage suited to each bias method type can be incorporated. Using this mask option reduces the number of components to add to the device, resulting in board space saving. The mask options provided in the PD78064 subseries are shown in Table 1-1. Table 1-1. Mask Options of Mask ROM Versions Pin names VLC0-VLC2 Mask options Split register can be incorporated. 12 User's Manual U10105EJ4V1UM00 CHAPTER 2 OUTLINE (PD78064Y Subseries) * 2.1 Features q On-chip high-capacity ROM and RAM Type Part Number Program Memory (ROM) 16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes (Note) 1024 bytes (Note) Data Memory Internal High-Speed RAM 512 bytes 1024 bytes LCD RAM 40 x 4 bytes PD78062Y PD78063Y PD78064Y PD78P064Y Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register. q Instruction execution time changeable from high speed (0.4 s: In main system clock 5.0 MHz operation) to ultralow speed (122 s: In subsystem clock 32.768 kHz operation) q Instruction set suited to system control * Bit manipulation possible in all address spaces * Multiply and divide instructions q Fifty-seven I/O ports (including alternative function pins for segment signal output) q LCD Controller / Driver * Segment signal output: * Common signal output: * Bias: * Power supply voltage: Max. 40 Max. 4 VDD = 2.0 to 6.0 V (Static display mode) VDD = 2.5 to 6.0 V (1/3 bias method) VDD = 2.7 to 6.0 V (1/2 bias method) q 8-bit resolution A/D converter: 8 channels q Serial interface: 2 channels * 3-wire//2-wire/I2C bus mode: 1 channel * 3-wire/UART mode: 1 channel q Timer: 5 channels * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Watch timer : 1 channel * Watchdog timer : 1 channel q Twenty vectored interrupts q Two test inputs q Two types of on-chip clock oscillators (main system clock and subsystem clock) q Power supply voltage: VDD = 2.0 to 6.0 V 1/2, 1/3 bias switching possible User's Manual U10105EJ4V1UM00 13 CHAPTER 2 OUTLINE (PD78064Y Subseries) 2.2 Applications Cellular phones, CD players, cameras, audio equipment, etc. 2.3 Ordering Information Part number Package 100-pin plastic QFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin ceramic WQFN Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One-time PROM One-time PROM EPROM PD78062YGC-xxx-7EA PD78062YGF-xxx-3BA PD78063YGC-xxx-7EA PD78063YGF-xxx-3BA PD78064YGC-xxx-7EA PD78064YGF-xxx-3BA PD78P064YGC-7EA* PD78P064YGF-3BA* PD78P064YKL-T* * : Under development xxx indicates ROM code suffix. Remark 14 User's Manual U10105EJ4V1UM00 CHAPTER 2 OUTLINE (PD78064Y Subseries) 2.4 Pin Configuration (Top View) (1) Normal operating mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm) PD78062YGC-xxx-7EA, 78063YGC-xxx-7EA, 78064YGC-xxx-7EA, 78P064YGC-7EA* P10/ANI0 AVSS P117 P116 P115 P114 P113 P112 P111 P110 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET XT2 XT1/P07 VDD X1 X2 IC (VPP) P72/SCK2/ASCK P71/SO2/TxD P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P100 P101 VSS P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 COM0 COM1 COM2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P70/SI2/RxD P27/SCK0/SCL P26/SO0/SB1/SDA1 P25/SI0/SB0/SDA0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19 * : Under development Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly. 2. Connect AVDD pin to VDD. 3. Connect AVSS pin to VSS. Remark Pin connection in parentheses is intended for the PD78P064Y. COM3 BIAS VLC0 VLC1 VLC2 VSS S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 User's Manual U10105EJ4V1UM00 15 CHAPTER 2 OUTLINE (PD78064Y Subseries) 100-pin plastic QFP (14 x 20 mm) PD78062YGF-xxx-3BA, 78063YGF-xxx-3BA, 78064YGF-xxx-3BA, 78P064YGF-3BA* 100-pin ceramic WQFN PD78P064YKL-T* P25/SI0/SB0/SDA0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 P26/SO0/SB1/SDA1 P27/SCK0/SCL P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK IC (VPP) X2 X1 VDD XT1/P07 XT2 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P110 P111 P112 P113 P114 P115 P116 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 VSS VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0 * : Under development Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly. 2. Connect AVDD pin to VDD. 3. Connect AVSS pin to VSS. Remark Pin connection in parentheses is intended for the PD78P064Y. 16 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P100 P101 VSS P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 User's Manual U10105EJ4V1UM00 CHAPTER 2 OUTLINE (PD78064Y Subseries) P00 to P05, P07 P10 to P17 P25 to P27 P30 to P37 P70 to P72 P80 to P87 P90 to P97 P100 to P103 P110 to P117 INTP0 to INTP5 TI00, TI01 TI1, TI2 TO0 to TO2 SB0, SB1 SI0 to SI2 SO0 to SO2 SCK0 to SCK2 SDA0, SDA1 SCL RxD : : : : : : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 7 Port 8 Port 9 Port 10 Port 11 Interrupt from Peripherals Timer Input Timer Input Timer Output Serial Bus Serial Input Serial Output Serial Clock Serial Data Serial Clock Receive Data TxD ASCK PCL BUZ S0 to S39 COM0 to COM3 VLC0 to VLC2 BIAS X1, X2 XT1, XT2 RESET ANI0 to ANI7 AVDD AVSS AVREF VDD VPP VSS IC : : : : : : : : : : : : : : : : : : : Transmit Data Asynchronous Serial Clock Programmable Clock Buzzer Clock Segment Output Common Output LCD Power Supply LCD Power Supply Bias Control Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Programming Power Supply Ground Internally Connected User's Manual U10105EJ4V1UM00 17 CHAPTER 2 OUTLINE (PD78064Y Subseries) (2) PROM programming mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm) PD78P064YGC-7EA* PGM (L) A9 RESET Open (L) VDD (L) Open VPP (L) (L) (L) VDD VSS (L) VSS (L) D0 D1 D2 D3 D4 D5 D6 D7 (L) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CE OE (L) (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) * : Under development Cautions 1. (L) 2. VSS 4. Open : Connect individually to VSS via a pull-down resistor. : Connect to the ground. : Do not connect anything. 3. RESET : Set to the low level. 18 User's Manual U10105EJ4V1UM00 (L) CHAPTER 2 OUTLINE (PD78064Y Subseries) 100-pin plastic QFP (14 x 20 mm) PD78P064YGF-3BA* 100-pin ceramic WQFN PD78P064YKL-T* (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) (L) VPP Open (L) VDD (L) Open RESET A9 (L) PGM (L) OE CE (L) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (L) VDD VSS VSS (L) * : Under development Cautions 1. (L) 2. VSS 4. Open A0 to A16 D0 to D7 CE OE PGM : Connect individually to VSS via a pull-down resistor. : Connect to the ground. : Do not connect anything. RESET VDD VPP VSS : Reset : Power Supply : Programming Power Supply : Ground 3. RESET : Set to the low level. : Address Bus : Data Bus : Chip Enable : Output Enable : Program (L) (L) D0 D1 D2 D3 D4 D5 D6 D7 User's Manual U10105EJ4V1UM00 19 CHAPTER 2 OUTLINE (PD78064Y Subseries) * 2.5 78K/0 Series Expansion 78K/0 series products evolution is illustrated below. Part numbers in the boxes indicates subseries names. Mass-produced Under development Y subseries supports I2C bus specifications. Performs control. 100-pin 100-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin PD78078 PD78070A PD78054 PD78018F PD78014 PD780001 PD78002 PD78083 Drives VFD (FIPs TM ). 78K/0 series 100-pin 80-pin 64-pin PD780208 PD78044A PD78024 Drives LCDs. 100-pin PD78064 PD78064Y Subseries for driving LCDs, has UART. Enhances I/O, FIP C/D based on PD78044A : Max. 53 display outputs Adds 6-bit U/D counter based on PD78024 : Max. 34 display outputs Basic subseries for driving FIPs : Max. 26 display outputs PD78002Y PD78078Y PD78070AY PD78054Y PD78018FY PD78014Y Adds timers and enhances external interface based on PD78054. ROM-less version of PD78078. Adds UART and D/A and enhances I/Os based on PD78014. Adds A/D and 16-bit timer based on PD78002. Adds A/D based on PD78002. Basic subseries for control applications Operates at 1.8 V and has UART. . Operates at 1.8 V and enhances ROM/RAM size selection based on PD78014 Supports IEBus.TM 80-pin PD78098 Adds IEBus controller based on PD78054. 20 User's Manual U10105EJ4V1UM00 CHAPTER 2 OUTLINE (PD78064Y Subseries) Major differences among these subseries are tabulated below. Function Subseries Control PD78078 PD78070A PD78054 PD78018F PD78014 PD780001 PD78002 PD78083 FIP drive PD780208 PD78024 LCD drive IEbus Support PD78098 32K-60K 2ch 1ch 1ch 1ch 8ch 2ch 3ch(UART:1ch) 69 2.7 V PD78064 ROM Timer 8-bit A/D 8ch 8-bit D/A 2ch 3ch(UART:1ch) 88 61 2ch -- 2ch 69 53 Serial Interface I/O VDD MIN 1.8 V 2.7 V 2.0 V 1.8 V 2.7 V -- -- 1ch -- 2ch 1ch 1ch 1ch -- 8ch 8ch -- 1ch 1ch (UART:1ch) 2ch 39 53 33 74 68 54 2ch 1ch 1ch 1ch 8ch -- 2ch(UART:1ch) 57 2.0 V -- 1.8 V 2.7 V -- -- -- External extension capacity 8-bit 16-bit Watch Watchdog 32K-60K -- 16K-60K 8K-48K 8K-32K 8K 8K-16K 32K-40K 4ch 1ch 1ch 1ch PD78044A 16K-40K 24K-32K 16K-32K User's Manual U10105EJ4V1UM00 21 CHAPTER 2 OUTLINE (PD78064Y Subseries) 2.6 Block Diagram TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 P00 P01-P05 P07 8-bit Timer/ Event Counter 1 16-bit Timer/ Event Counter Port 0 Port 1 P10-P17 Port 2 8-bit Timer/ Event Counter 2 P25-P27 Port 3 Watchdog Timer Port 7 P30-P37 P70-P72 Watch Timer Port 8 78K/0 CPU Core P80-P87 SDA0/SI0/SB0/P25 SDA1/SO0/SB1/P26 SCL/SCK0/P27 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 Serial Interface 2 Serial Interface 0 ROM Port 9 P90-P97 Port 10 P100-P103 Port 11 P110-P117 S0-S23 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/P00INTP5/P05 A/D Converter RAM LCD Controller/ Driver S24/P97S31/P90 S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD RESET X1 X2 XT1/P07 XT2 Interrupt Control BUZ/P36 Buzzer Output System Control PCL/P35 Clock Output Control VDD VSS IC (VPP) Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the PD78P064. 22 User's Manual U10105EJ4V1UM00 CHAPTER 2 OUTLINE (PD78064Y Subseries) 2.7 Outline of Function PD78062Y PD78063Y PD78064Y PD78P064YNote1 Part Number Item Internal memory ROM Mask ROM 16 Kbytes 24 Kbytes 1024 bytes 32 Kbytes PROM 32 KbytesNote2 1024 bytesNote2 Internal high-speed RAM LCD RAM General register Instruction With main system clock selected Cycle With subsystem clock selected 512 bytes 40 x 4 bits 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0 MHz) 122 s (@ 32.768 kHz) * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulate (set, reset, test, and Boolean operation) * BCD adjust, etc. Instruction set I/O port (including alternative function pins for segment signal output) * Total * CMOS input * CMOS I/O : 57 :2 : 55 A/D converter LCD controller / driver 8-bit resolution x 8 channels * Segment signal output: Max. 40 * Common signal output: Max. 4 * Bias: 1/2, 1/3 bias switching possible Serial interface * 3-wire/2-wire/I2C bus mode selection possible: 1 channel * 3-wire mode / UART mode selection possible: 1 channel Timer * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter * Watch timer * Watchdog timer Timer output Clock output : 2 channels : 1 channel : 1 channel Three outputs: (14-bit PWM output enable: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock) 32.768 kHz (@ 32.768 kHz with subsystem clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock) Notes 1. Under development 2. The capacities of the internal PROM and the internal high-speed RAM can be changed using the memory switching register. User's Manual U10105EJ4V1UM00 23 CHAPTER 2 OUTLINE (PD78064Y Subseries) Part Number Item Maskable interrupt Vectored interrupt Non-maskable interrupt Software interrupt Test input PD78062Y PD78063Y PD78064Y PD78P064YNote Internal: 12 External: 6 Internal: 1 Internal: 1 Internal: 1 External: 1 Power supply voltage Operating ambient temperature Package VDD = 2.0 to 6.0 V TA = -40 to +85 C * 100-pin plastic QFP (Fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFN (PD78P064Y only) Note Under development 2.8 Mask Options The mask ROM versions (PD78062Y, 78063Y, 78064Y) provide split resistor mask options. By specifying this mask options at the time of ordering, split registers which enable to generate LCD drive voltage suited to each bias method type can be incorporated. Using this mask option reduces the number of components to add to the device, resulting in board space saving. The mask options provided in the PD78064Y subseries are shown in Table 2-1. Table 2-1. Mask Options of Mask ROM Versions Pin names VLC0-VLC2 Mask options Split register can be incorporated. 24 User's Manual U10105EJ4V1UM00 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/2) Pin Name Input/Output P00 P01 P02 P03 P04 P05 P07Note1 P10 to P17 Input Input/ output Port 1. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as input port, a pull-up resistor can be connected by softwareNote2. P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 Input/ output Input/ output/ Port 2. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Port 3. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Input SO0/SB1 SCK0 TO0 TO1 TO2 TI1 TI2 PCL BUZ -- Input SI0/SB0 Input Input/ output Port 0. 7-bit input/output port. Function Input only Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Input only Input Input After Reset Alternative Function Input Input INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7 Notes 1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register to 1 (do not use the feedback resistor internal to the subsystem clock oscillator). 2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, the pull-up resistor is automatically disabled. User's Manual U10105EJ4V1UM00 25 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) (1) Port pins (2/2) Pin Name Input/Output P70 P71 P72 P80 to P87 Input/ output Input/ output Port 7. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Port 8. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. I/O port / segment signal output can be specified in 2-bit units by LCD control register. P90 to P97 Input/ output Port 9. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. I/O port / segment signal output can be specified in 2-bit units by LCD control register. P100 to P103 Input/ output Port 10. 4-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. A resistor can be connected. LED can be driven directly. P110 to 117 Input/ Output Port 11. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Falling edge can be detected. Input -- Input -- Input S31 to S24 Input SCK2/ASCK S39 to S32 Function After Reset Alternative Function Input SI2/RxD SO2/TxD 26 User's Manual U10105EJ4V1UM00 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) (2) Pins other than port pins (1/2) Pin Name Input/Output INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI2 SO0 SO2 SB0 SB1 SCK0 SCK2 RxD TxD ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ S0 to S23 S24 to S31 S32 to S39 COM0-COM3 Output VLC0 to VLC2 -- Common signal output of LCD controller/driver LCD drive voltage (mask ROM versions can incorporate dividing resistor (mask option.)) BIAS ANI0 to ANI7 AVREF AVDD -- Input Input -- Power supply for LCD drive A/D converter analog input D/A converter analog output A/D converter reference voltage input -- Input -- -- -- P10 to P17 -- -- Output -- Output Output Output Clock output (for main system clock and subsystem clock trimming) Buzzer output Segment signal output of LCD controller/driver Input Input Output Input Output Input/ output Input/ output Input Output Input Input Asynchronous serial interface serial data input Asynchronous serial interface serial data output Asynchronous serial interface serial clock input External count clock input to 16-bit timer (TM0) Capture trigger signal input to capture register (CR00) External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2) 16-bit timer output (also used for 14-bit PWM output) 8-bit timer output Input Input Input Input Input Serial interface serial clock input/output Input Serial interface serial data input/output Input Output Serial interface serial data output Input Input Serial interface serial data input Input Input Function External interrupt inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). After Reset Alternative Function Input P00/TI00 P01/TI01 P02 P03 P04 P05 P25/SB0 P70/RxD P26/SB1 P71/TxD P25/SI0 P26/SO0 P27 P72/ASCK P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P33 P34 P30 P31 P32 P35 P36 -- P97 to P90 P87 to P80 -- -- User's Manual U10105EJ4V1UM00 27 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) (2) Pins other than port pins (2/2) Pin Name Input/Output AVSS RESET X1 X2 XT1 XT2 VDD -- Input Input -- Input -- -- -- Positive power supply High-voltage application for program write/verify. Connect directly to VSS in normal operating mode. VSS IC -- -- Ground potential Internal connection. Connect directly to VSS. -- -- -- -- Crystal connection for subsystem clock oscillation Function A/D converter ground potential. Connect to VSS. System reset input Crystal connection for main system clock oscillation After Reset Alternative Function -- -- -- -- Input -- -- -- -- -- -- -- P07 -- -- -- * VPP 3.1.2 PROM programming mode pins (PD78P064 only) Pin Name Input/Output RESET Input Function PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin, the PROM programming mode is set. VPP A0 to A16 D0 to D7 CE OE PGM VDD VSS Input Input High-voltage application for PROM programming mode setting and program write/verify. Address bus Input/output Data bus Input Input Input -- -- PROM enable input/program pulse input Read strobe input to PROM Program/program inhibit input in PROM programming mode Positive power supply Ground potential 28 User's Manual U10105EJ4V1UM00 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.2 Description of Pin Functions 3.2.1 P00 to P05, P07 (Port 0) These are 7-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem clock oscillation. The following operating modes can be specified bit-wise. (1) Port mode P00 and P07 function as input-only ports and P01 to P05 function as input/output ports. P01 to P05 can be specified for input or output ports bit-wise with a port mode register 0. When they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register L. (2) Control mode In this mode, these ports function as an external interrupt input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) INTP0 to INTP5 INTP0 to INTP5 are external interrupt input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. (b) TI00 Pin for external count clock input to 16-bit timer/event counter (c) TI01 Pin for capture trigger signal input to capture register (CR00) of 16-bit timer/event counter (d) XT1 Crystal connect pin for subsystem clock oscillation User's Manual U10105EJ4V1UM00 29 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with a port mode register 1. If used as input ports, pull-up resistors can be connected to these ports by defining the pull-up resistor option register L. (2) Control mode These ports function as A/D converter analog input pins (ANI0-ANI7). The pull-up resistor is automatically disabled when the pins specified for analog input. 3.2.3 P25 to P27 (Port 2) These are 3-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface and clock input/output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 3-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 2. When they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register L. (2) Control mode These ports function as serial interface data input/output and clock input/output. (a) SI0, SO0 Serial interface serial data input/output pins (b) SCK0 Serial interface serial clock input/output pins (c) SB0 and SB1 NEC standard serial bus interface input/output pins Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires. For the setting, refer to Figure 15-4 "Serial Operation Mode Register 0 Format". 30 User's Manual U10105EJ4V1UM00 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register L. (2) Control mode These ports function as timer input/output, clock output, and buzzer output. (a) TI1 and TI2 Pin for external clock input to the 8-bit timer/event counter. (b) TO0 to TO2 Timer output pins. (c) PCL Clock output pin. (d) BUZ Buzzer output pin. User's Manual U10105EJ4V1UM00 31 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.2.5 P70 to P72 (Port 7) These are 3-bit input/output ports. Beside serving as input/output ports, they function as serial interface data input/ output, clock input/output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 3-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 7. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register L. (2) Control mode These ports function as serial interface data input/output and clock input/output. (a) SI2, SO2 Serial interface serial data input/output pins (b) SCK2 Serial interface serial clock input/output pin. (c) RxD, TxD Asynchronous serial interface serial data input/output pins. (d) ASCK Asynchronous serial interface serial clock input pin. * Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires. For the setting, see the operation mode setting list in Table 17-2 "Serial Interface Channel 2". 32 User's Manual U10105EJ4V1UM00 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.2.6 P80-P87 (Port 8) These are 8-bit input/output ports. Beside serving as input/output ports, they function as segment signal output of LCD controller/driver. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 8. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register H. (2) Control mode These ports function as segment signal output pins (S32 to S39) of LCD controller/driver. 3.2.7 P90-P97 (Port 9) These are 8-bit input/output ports. Beside serving as input/output ports, they function as segment signal output of LCD controller/driver. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 9. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register H. (2) Control mode These ports function as segment signal/output pins (S24 to S31) of LCD controller/driver. 3.2.8 P100-P103 (Port 10) These ports function as 4-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 10. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register H. LED can be driven directly. 3.2.9 P110-P117 (Port 11) These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 11. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register H. Test input flag (KRIF) can be set to 1 by detecting falling edges. User's Manual U10105EJ4V1UM00 33 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.2.10 COM0 to COM3 These are LCD controller/driver common signal output pins. They output common signals under either of the following conditions: - when the static mode is selected (COM0 to COM3 outputs) - when 2-time-division (COM0, COM1 outputs) or 3-time-division (COM0 to COM2 outputs) operation is performed in 1/2 bias mode - when 3-time-division (COM0 to COM2 outputs) or 4-time-division (COM0 to COM3 outputs) operation is performed in 1/3 bias mode 3.2.11 VLC0-VLC2 These are LCD-driving voltage pins. The mask ROM versions can have split resistors by mask option so that LCD driving voltage can be supplied inside the VLC0-VLC2 pins according to the required bias without connecting external split resistors. 3.2.12 BIAS These are LCD driving power supply pins. They should be connected to the VLC0 pin to realize user-desired LCD drive voltages to change resistance division ratios, or should be connected to external resistors together with the VLC0-VLC2 pins and VSS pin to fine-adjust the LCD-driving power voltage. 3.2.13 AVREF This pin inputs the reference voltage for the on-chip A/D converter. When not using the A/D converter,connect this pin to the VSS line. 3.2.14 AVDD This pin supplies analog voltage for the on-chip A/D converter. Even when not using the A/D converter, always use this pin at the same voltage as VDD. 3.2.15 AVSS This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when A/D converter is not used. 3.2.16 RESET This is a low-level active system reset input pin. 3.2.17 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2. 3.2.18 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 34 User's Manual U10105EJ4V1UM00 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.2.19 VDD Positive power supply pin 3.2.20 VSS Ground potential pin 3.2.21 VPP (PD78P064 only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to VSS in normal operating mode. 3.2.22 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD78064 subseries at delivery. Connect it directly to the VSS with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally. q Connect IC pins to VSS pins directly. VSS IC As short as possible User's Manual U10105EJ4V1UM00 35 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) 3.3 Input/output Circuits and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1. Pin Input/Output Circuit Types (1/2) Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 Input/Output Circuit Type 2 8-A Input/Output Input Input/Output Recommended Connection of Unused Pins Connect to VSS. Connect independently via a resistor to VSS. * P07/XT1 P10/ANI0 to P17/ANI7 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/S39-P87/S32 P90/S31-P97/S24 P100-P103 16 11 10-A Input Input/Output Connect to VDD. Connect independently via a resistor to VDD or VSS. 5-A 8-A 5-A 8-A 5-A 8-A 17-A 5-A 8-A 17 18 -- -- Output Connect to VSS. Open * P110-P117 S0-S23 COM0-COM3 VLC0-VLC2 BIAS RESET XT2 2 16 Input -- -- Open 36 User's Manual U10105EJ4V1UM00 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name AVREF AVDD AVSS IC (Mask ROM version) VPP (PD78P064 version) Input/Output Circuit Type -- Input/Output -- Recommended Connection of Unused Pins Connect to VSS. Connect to VDD. Connect to VSS. Connect directly to VSS. * User's Manual U10105EJ4V1UM00 37 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) Figure 3-1. Pin Input/Output Circuit of List (1/2) Type 2 Type 10-A VDD pullup enable VDD IN data P-ch P-ch IN/OUT open drain output disable Schmitt-triggered input with hysteresis characteristics N-ch Type 5-A VDD Type 11 pullup enable VDD P-ch VDD P-ch IN/OUT pullup enable data P-ch VDD P-ch IN/OUT data output disable input enable Type 8-A N-ch output disable Comparator N-ch P-ch + - N-ch VREF (Threshold voltage) input enable Type 16 VDD feedback cut-off P-ch pullup enable data P-ch VDD P-ch IN/OUT output disable N-ch XT1 XT2 38 User's Manual U10105EJ4V1UM00 CHAPTER 3 PIN FUNCTION (PD78064 Subseries) Figure 3-1. Pin Input/Output Circuit of List (2/2) Type 17 Type 17-A VDD VLC0 VLC1 P-ch N-ch SEG data P-ch VLC2 N-ch N-ch output disable N-ch P-ch OUT data pullup enable P-ch VDD P-ch IN/OUT Type 18 VLC0 P-ch VLC1 N-ch P-ch N-ch input enable VLC0 P-ch VLC1 N-ch SEG data P-ch OUT N-ch P-ch P-ch VLC2 N-ch N-ch P-ch COM data VLC2 N-ch User's Manual U10105EJ4V1UM00 39 [MEMO] 40 User's Manual U10105EJ4V1UM00 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) * 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/2) Pin Name Input/Output P00 P01 P02 P03 P04 P05 P07Note1 P10 to P17 Input Input/ output Port 1. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as input port, a pull-up resistor can be connected by softwareNote2. P25 P26 Input/output mode can be specified bit-wise. P27 P30 P31 P32 P33 P34 P35 P36 P37 Input/ output If used as an input port, a pull-up resistor can be connected by software. Port 3. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Input SCK0/SCL TO0 TO1 TO2 TI1 TI2 PCL BUZ -- Input output/ Port 2. 3-bit input/output port. SO0/SB1/SDA1 Input SI0/SB0/SDA0 Input Input/ output Port 0. 7-bit input/output port. Function Input only Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Input only Input Input After Reset Alternative Function Input Input INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7 Notes 1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register to 1 (do not use the feedback resistor internal to the subsystem clock oscillator). 2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, the pull-up resistor is automatically disabled. User's Manual U10105EJ4V1UM00 41 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) (1) Port pins (2/2) Pin Name Input/Output P70 P71 P72 If used as an input port, a pull-up resistor can be connected by software. P80 to P87 Input/ output Port 8. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. I/O port / segment signal output can be specified in 2-bit units by LCD control register. P90 to P97 Input/ output Port 9. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. I/O port / segment signal output can be specified in 2-bit units by LCD control register. P100 to P103 Input/ output Port 10. 4-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. A resistor can be connected. LED can be driven directly. P110 to 117 Input/ Output Port 11. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Falling edge can be detected. Input -- Input -- Input S31 to S24 Input S39 to S32 Input/ output Port 7. 3-bit input/output port. Input/output mode can be specified bit-wise. SCK2/ASCK Function After Reset Alternative Function Input SI2/RxD SO2/TxD 42 User's Manual U10105EJ4V1UM00 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) (2) Pins other than port pins (1/2) Pin Name Input/Output INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI2 SO0 SO2 SB0 SB1 SDA0 SDA1 SCK0 SCK2 SCL RxD TxD ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ S0 to S23 S24 to S31 S32 to S39 COM0 to COM3 Output VLC0 to VLC2 -- Common signal output of LCD controller/driver LCD drive voltage (mask ROM versions can incorporate dividing resistor (mask option).) BIAS ANI0 to ANI7 AVREF AVDD -- Input Input -- Power supply for LCD drive A/D converter analog input A/D converter analog output A/D converter reference voltage input -- Input -- -- -- P10 to P17 -- -- Output -- Output Output Output Clock output (for main system clock and subsystem clock trimming) Buzzer output Segment signal output of LCD controller/driver Input Input Output Input Output Input Output Input Input Asynchronous serial interface serial data input Asynchronous serial interface serial data output Asynchronous serial interface serial clock input External count clock input to 16-bit timer (TM0) Capture trigger signal input to capture register (CR00) External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2) 16-bit timer output (also used for 14-bit PWM output) 8-bit timer output Input Input Input Input Input Input/ output Serial interface serial clock input/output Input Input/ output Serial interface serial data input/output Input Output Serial interface serial data output Input Input Serial interface serial data input Input Input Function External interrupt inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). After Reset Alternative Function Input P00/TI00 P01/TI01 P02 P03 P04 P05 P25/SB0/SDA0 P70/RxD P26/SB1/SDA1 P71/TxD P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P72/ASCK P27/SCK0 P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P33 P34 P30 P31 P32 P35 P36 -- P97 to P90 P87 to P80 -- -- User's Manual U10105EJ4V1UM00 43 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) (2) Pins other than port pins (2/2) Pin Name Input/Output AVSS RESET X1 X2 XT1 XT2 VDD VPP -- Input Input -- Input -- -- -- Positive power supply High-voltage application for program write/verify. Connect directly to VSS in normal operating mode. VSS IC -- -- Ground potential Internal connection. Connect directly to VSS. -- -- -- -- Crystal connection for subsystem clock oscillation Function A/D converter ground potential. Connect to VSS. System reset input Crystal connection for main system clock oscillation After Reset Alternative Function -- -- -- -- Input -- -- -- -- -- -- -- P07 -- -- -- 4.1.2 PROM programming mode pins (PD78P064Y only) Pin Name Input/Output RESET Input Function PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin, the PROM programming mode is set. VPP A0 to A16 D0 to D7 CE OE PGM VDD VSS Input Input High-voltage application for PROM programming mode setting and program write/verify. Address bus Input/output Data bus Input Input Input -- -- PROM enable input/program pulse input Read strobe input to PROM Program/program inhibit input in PROM programming mode Positive power supply Ground potential 44 User's Manual U10105EJ4V1UM00 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) 4.2 Description of Pin Functions 4.2.1 P00 to P05, P07 (Port 0) These are 7-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem clock oscillation. The following operating modes can be specified bit-wise. (1) Port mode P00 and P07 function as input-only ports and P01 to P05 function as input/output ports. P01 to P05 can be specified for input or output ports bit-wise with a port mode register 0. When they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register L. (2) Control mode In this mode, these ports function as an external interrupt input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) INTP0 to INTP5 INTP0 to INTP5 are external interrupt input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. (b) TI00 Pin for external count clock input to 16-bit timer/event counter (c) TI01 Pin for capture trigger signal input to capture register (CR00) of 16-bit timer/event counter (d) XT1 Crystal connect pin for subsystem clock oscillation User's Manual U10105EJ4V1UM00 45 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with a port mode register 1. If used as input ports, pull-up resistors can be connected to these ports by defining the pull-up resistor option register L. (2) Control mode These ports function as A/D converter analog input pins (ANI0-ANI7). The pull-up resistor is automatically disabled when the pins specified for analog input. 4.2.3 P25 to P27 (Port 2) These are 3-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface and clock input/output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 3-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 2. When they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register L. (2) Control mode These ports function as serial interface data input/output and clock input/output. (a) SI0, SO0, SB0, SB1, SDA0, SDA1 Serial interface serial data input/output pins (b) SCK0, SCL Serial interface serial clock input/output pins Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires. For the setting, refer to Figure 16-4 "Serial Operation Mode Register 0 Format". 46 User's Manual U10105EJ4V1UM00 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register L. (2) Control mode These ports function as timer input/output, clock output, and buzzer output. (a) TI1 and TI2 Pin for external clock input to the 8-bit timer/event counter. (b) TO0 to TO2 Timer output pins. (c) PCL Clock output pin. (d) BUZ Buzzer output pin. User's Manual U10105EJ4V1UM00 47 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) 4.2.5 P70 to P72 (Port 7) These are 3-bit input/output ports. Beside serving as input/output ports, they function as serial interface data input/ output, clock input/output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 3-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 7. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register L. (2) Control mode These ports function as serial interface data input/output and clock input/output. (a) SI2, SO2 Serial interface serial data input/output pins (b) SCK2 Serial interface serial clock input/output pin. (c) RxD, TxD Asynchronous serial interface serial data input/output pins. (d) ASCK Asynchronous serial interface serial clock input pin. Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires. For the setting, see the operation mode setting list in Table 17-2 "Serial Interface Channel 2" 48 User's Manual U10105EJ4V1UM00 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) 4.2.6 P80-P87 (Port 8) These are 8-bit input/output ports. Beside serving as input/output ports, they function as segment signal output of LCD controller/driver. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 8. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register H. (2) Control mode These ports function as segment signal output pins (S32 to S39) of LCD controller/driver. 4.2.7 P90-P97 (Port 9) These are 8-bit input/output ports. Beside serving as input/output ports, they function as segment signal output of LCD controller/driver. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 9. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register H. (2) Control mode These ports function as segment signal output pins (S24 to S31) of LCD controller/driver. 4.2.8 P100-P103 (Port 10) These are 4-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 10. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register H. LED can be driven directly. 4.2.9 P110-P117 (Port 11) These are 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 11. When they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register H. Test input flag (KRIF) can be set to 1 by detecting falling edges. User's Manual U10105EJ4V1UM00 49 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) 4.2.10 COM0 to COM3 These are LCD controller/driver common signal output pins. They output common signals under either of the following conditions: - when the static mode is selected (COM0 to COM3 outputs) - when 2-time-division (COM0, COM1 outputs) or 3-time-division (COM0 to COM2 outputs) operation is performed in 1/2 bias mode - when 3-time-division (COM0 to COM2 outputs) or 4-time-division (COM0 to COM3 outputs) operation is performed in 1/3 bias mode 4.2.11 VLC0-VLC2 These are LCD-driving voltage pins. The mask ROM versions can have split resistors by mask option so that LCD driving voltage can be supplied inside the VLC0-VLC2 pins according to the required bias without connecting external split resistors. 4.2.12 BIAS These are LCD driving power supply pins. They should be connected to the VLC0 pin to realize user-desired LCD drive voltages to change resistance division ratios, or should be connected to external resistors together with the VLC0-VLC2 pins and VSS pin to fine-adjust the LCD-driving power voltage. 4.2.13 AVREF This pin inputs the reference voltage for the on-chip A/D converter. When not using the A/D converter,connect this pin to the VSS line. 4.2.14 AVDD This pin supplies analog voltage for the on-chip A/D converter. Even when not using the A/D converter, always use this pin at the same voltage as VDD. 4.2.15 AVSS This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when A/D converter is not used. 4.2.16 RESET This is a low-level active system reset input pin. 4.2.17 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2. 4.2.18 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 50 User's Manual U10105EJ4V1UM00 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) 4.2.19 VDD Positive power supply pin 4.2.20 VSS Ground potential pin 4.2.21 VPP (PD78P064Y only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to VSS in normal operating mode. 4.2.22 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD78064Y subseries at delivery. Connect it directly to the VSS with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally. q Connect IC pins to VSS pins directly. VSS IC As short as possible User's Manual U10105EJ4V1UM00 51 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) 4.3 Input/output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1. Pin Input/Output Circuit Types (1/2) Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0 to P17/ANI7 P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/S39-P87/S32 P90/S31-P97/S24 P100-P103 5-A 8-A 17 18 -- -- Output Connect independently via a resistor to VDD. Open 8-A 5-A 8-A 17-A 5-A 8-A 5-A 16 11 10-A Input Input/Output Connect to VDD. Connect independently via a resistor to VDD or VSS. Input/Output Circuit Type 2 8-A Input/Output Input Input/Output Recommended Connection of Unused Pins Connect to VSS. Connect independently via a resistor to VSS. * P110-P117 S0-S23 COM0-COM3 VLC0-VLC2 BIAS RESET XT2 2 16 Input -- -- Open 52 User's Manual U10105EJ4V1UM00 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name AVREF AVDD AVSS IC (Mask ROM version) VPP (PD78P064Y version) Input/Output Circuit Type -- Input/Output -- Recommended Connection of Unused Pins Connect to VSS. Connect to VDD. Connect to VSS. Connect directly to VSS. User's Manual U10105EJ4V1UM00 53 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) Figure 4-1. Pin Input/Output Circuit of List (1/2) Type 2 Type 10-A VDD pullup enable VDD IN data P-ch P-ch IN/OUT open drain output disable Schmitt-triggered input with hysteresis characteristics N-ch Type 5-A VDD Type 11 pullup enable VDD P-ch VDD P-ch IN/OUT pullup enable data P-ch VDD P-ch IN/OUT data output disable input enable Type 8-A N-ch output disable Comparator N-ch P-ch + - N-ch VREF (Threshold voltage) input enable Type 16 VDD feedback cut-off P-ch pullup enable data P-ch VDD P-ch IN/OUT output disable N-ch XT1 XT2 54 User's Manual U10105EJ4V1UM00 CHAPTER 4 PIN FUNCTION (PD78064Y Subseries) Figure 4-1. Pin Input/Output Circuit of List (2/2) Type 17 Type 17-A VDD VLC0 VLC1 P-ch N-ch SEG data P-ch VLC2 N-ch N-ch output disable N-ch P-ch OUT data pullup enable P-ch VDD P-ch IN/OUT Type 18 VLC0 P-ch VLC1 N-ch P-ch N-ch input enable VLC0 P-ch VLC1 N-ch SEG data P-ch OUT N-ch P-ch P-ch VLC2 N-ch N-ch P-ch COM data VLC2 N-ch User's Manual U10105EJ4V1UM00 55 [MEMO] 56 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces Figures 5-1 to 5-4 shows memory maps. Figure 5-1. Memory Map (PD78062, 78062Y) FFFFH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits General Registers 32 x 8 bits Internal High-speed RAM 512 x 8 bits FD00H FCFFH Reserved FA80H FA7FH FA58H FA57H 3FFFH LCD RAM 40 x 4 bits 1000H 0FFFH CALLF Entry Area Reserved 0800H 07FFH Program Area 0080H 007FH CALLT Table Area Internal ROM 16384 x 8 bits 0040H 003FH Vector Table Area 0000H 0000H Program Area Data memory space 4000H 3FFFH Program memory space User's Manual U10105EJ4V1UM00 57 CHAPTER 5 CPU ARCHITECTURE Figure 5-2. Memory Map (PD78063, 78063Y) FFFFH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits FB00H FAFFH Reserved FA80H FA7FH FA58H FA57H 5FFFH LCD RAM 40 x 4 bits 1000H 0FFFH CALLF Entry Area Reserved 0800H 07FFH Program Area 0080H 007FH CALLT Table Area Internal ROM 24576 x 8 bits 0040H 003FH Vector Table Area 0000H 0000H Program Area Data memory space 6000H 5FFFH Program memory space 58 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE Figure 5-3. Memory Map (PD78064, 78064Y) FFFFH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits FB00H FAFFH Reserved FA80H FA7FH FA58H FA57H 7FFFH LCD RAM 40 x 4 bits 1000H 0FFFH CALLF Entry Area Reserved 0800H 07FFH Program Area 0080H 007FH CALLT Table Area Internal ROM 32768 x 8 bits 0040H 003FH Vector Table Area 0000H 0000H Program Area Data memory space 8000H 7FFFH Program memory space User's Manual U10105EJ4V1UM00 59 CHAPTER 5 CPU ARCHITECTURE Figure 5-4. Memory Map (PD78P064, 78P064Y) FFFFH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits FB00H FAFFH Reserved FA80H FA7FH FA58H FA57H 7FFFH LCD RAM 40 x 4 bits 1000H 0FFFH CALLF Entry Area Reserved 0800H 07FFH Program Area 0080H 007FH CALLT Table Area Internal PROM 32768 x 8 bits 0040H 003FH Vector Table Area 0000H 0000H Program Area Data memory space 8000H 7FFFH Program memory space 60 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The internal program memory space stores program data and table data. This space is generally accessed with program counter (PC). The PD78064, 78064Y subseries has on chip ROM (or PROM) and the capacity of the memory varies depending on the part number. Table 5-1. Internal ROM Capacity Part number Type Internal ROM Capacity 16384 x 8 bits 24576 x 8 bits 32768 x 8 bits PROM PD78062, 78062Y PD78063, 78063Y PD78064, 78064Y PD78P064, 78P064Y Mask ROM The internal program memory is divided into the following three areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses. Table 5-2. Vector Table Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0014H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 003EH Interrupt Request RESET input INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTCSI0 INTSER INTSR/INTCSI2 INTST INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD BRK User's Manual U10105EJ4V1UM00 61 CHAPTER 5 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 5.1.2 Internal data memory space The PD78064 and 78064Y subseries units incorporate the following RAMs. (1) Internal high-speed RAM The PD78064, 78064Y subseries has on-chip high-speed RAM, and the memory capacity varies depending on the part number as shown below. Table 5-3. Internal High-Speed RAM Capacity Part number Internal high-speed RAM capacity 512 x 8 bits 1024 x 8 bits PD78062, 78062Y PD78063, 78063Y PD78064, 78064Y PD78P064, 78P064Y In this area, four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH. The internal high-speed RAM can also be used as a stack. (2) LCD display RAM Addresses FA58H to FA7FH of 40 x 4 bits are allocated for LCD display RAM, However, this area can also be used as general-purpose RAM. 5.1.3 Special Function Register (SFR) area An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH. (Refer to Table 5-4). Caution Do not access addresses where the SFR is not assigned. 62 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.1.4 Data memory addressing The PD78064, 78064Y subseries is provided with a variety of addressing modes which take account of memory manipulability, etc. Especially at addresses corresponding to data memory area, particular addressing modes are possible to meet the functions of the special function registers (SFRs) and general registers. This area is between FD00H and FFFFH for the PD78062 and 78062Y, and between FB00H and FFFFH for the other devices. Figures 5-5 to 5-8 show the data memory addressing modes. Figure 5-5. Data Memory Addressing (PD78062, 78062Y) FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 512 x 8 bits Register Addressing Short Direct Addressing FE20H FE1FH FD00H FCFFH Reserved FA80H FA7FH LCD RAM 40 x 4 bits FA58H FA57H Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing Reserved 4000H 3FFFH Internal ROM 16384 x 8 bits 0000H User's Manual U10105EJ4V1UM00 63 CHAPTER 5 CPU ARCHITECTURE Figure 5-6. Data Memory Addressing (PD78063, 78063Y) FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Register Addressing Short Direct Addressing FE20H FE1FH FB00H FAFFH Reserved FA80H FA7FH LCD RAM 40 x 4 bits FA58H FA57H Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing Reserved 6000H 5FFFH Internal ROM 24576 x 8 bits 0000H 64 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE Figure 5-7. Data Memory Addressing (PD78064, 78064Y) FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Register Addressing Short Direct Addressing FE20H FE1FH FB00H FAFFH Reserved FA80H FA7FH LCD RAM 40 x 4 bits FA58H FA57H Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing Reserved 8000H 7FFFH Internal ROM 32768 x 8 bits 0000H User's Manual U10105EJ4V1UM00 65 CHAPTER 5 CPU ARCHITECTURE Figure 5-8. Data Memory Addressing (PD78P064, 78P064Y) FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Register Addressing Short Direct Addressing FE20H FE1FH FB00H FAFFH Reserved FA80H FA7FH LCD RAM 40 x 4 bits FA58H FA57H Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing Reserved 8000H 7FFFH Internal PROM 32768 x 8 bits 0000H 66 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.2 Processor Registers The PD78064 and 78064Y subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter, a program status word and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 5-9. Program Counter Configuration 15 PC 0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 5-10. Program Status Word Configuration 7 IE Z RBS1 AC RBS0 0 ISP 0 CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to DI, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to EI and interrupt request acknowledge enable is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag. The IE is reset to (0) upon DI instruction execution or interrupt acknowledgement and is set to (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored. User's Manual U10105EJ4V1UM00 67 CHAPTER 5 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-level vectored interrupts specified with a priority specify flag register (PR) are disabled for acknowledgement. When it is 1, all interrupts are acknowledgeable. Actual acknowledgement is controlled with the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FD00H-FEFFH for the PD78062 and 78062Y, and FB00H-FEFFH for the other devices) can be set as the stack area. Figure 5-11. Stack Pointer Configuration 15 SP 0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 5-12 and 5-13. Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before instruction execution. Figure 5-12. Data to be Saved to Stack Memory Interrupt and BRK Instruction SP SP SP _ 2 SP _ 2 SP _ 1 SP Register Pair Lower Register Pair Upper SP SP _ 2 SP _ 2 SP _ 1 SP PC7-PC0 PC15-PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP PC7-PC0 PC15-PC8 PSW PUSH rp Instruction CALL, CALLF, and CALLT Instruction 68 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE Figure 5-13. Data to be Reset from Stack Memory RETI and RETB Instruction POP rp Instruction RET Instruction SP SP + 1 SP SP + 2 Register Pair Lower Register Pair Upper SP SP SP + 1 SP + 2 PC7-PC0 PC15-PC8 SP SP + 1 SP + 2 SP SP + 3 PC7-PC0 PC15-PC8 PSW 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE and HL). They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. User's Manual U10105EJ4V1UM00 69 CHAPTER 5 CPU ARCHITECTURE Figure 5-14. General Register Configuration (a) Absolute Name 16-Bit Processing FEFFH R7 BANK0 FEF8H RP3 R6 R5 BANK1 FEE0H RP2 R4 R3 BANK2 FEE8H RP1 R2 R1 BANK3 FEE0H 15 0 7 0 RP0 R0 8-Bit Processing (b) Function Name 16-Bit Processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H DE E B BANK2 FEE8H BC C A BANK3 FEE0H 15 0 7 0 AX X 8-Bit Processing 70 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special-function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, describe an even address. Table 5-4 gives a list of special-function registers. The meaning of items in the table is as follows. * Symbol This is a symbol used in assembler (RA78K/0) to indicate an address of the built-in special-function register. It is describable as an instruction operand. * R/W Indicates whether the corresponding special-function register can be read or written. R/W : Read/write enable R W : Read only : Write only * Manipulatable bit units Manipulatable bit units, 1, 8, and 16, are indicated. * After reset Indicates each register status upon RESET input. User's Manual U10105EJ4V1UM00 71 CHAPTER 5 CPU ARCHITECTURE Table 5-4. Special-Function Register List (1/3) Manipulatable Bit Unit Address FF00H FF01H FF02H FF03H FF07H FF08H FF09H FF0AH FF0BH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1FH FF20H FF21H FF22H FF23H FF27H FF28H FF29H FF2AH FF2BH FF40H FF41H FF42H FF43H FF47H FF48H Compare register 10 Compare register 20 8-bit timer register 1 TMS 8-bit timer register 2 Serial I/O shift register 0 A/D conversion result register Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 7 Port mode register 8 Port mode register 9 Port mode register 10 Port mode register 11 Timer clock select register 0 Timer clock select register 1 Timer clock select register 2 Timer clock select register 3 Sampling clock select register 16-bit timer mode control register TM2 SIO0 ADCR PM0 PM1 PM2 PM3 PM7 PM8 PM9 PM10 PM11 TCL0 TCL1 TCL2 TCL3 SCS TMC0 R/W R R/W -- -- -- -- -- -- -- CR10 CR20 TM1 R R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 88H 00H 00H FFH Undefined -- -- 00H Undefined 16-bit timer register TM0 R -- -- 00H Capture/compare register 01 CR01 -- -- Special-Function Register (SFR) Name Port0 Port1 Port2 Port3 Port7 Port8 Port9 Port10 Port11 Capture/compare register 00 Symbol P0 P1 P2 P3 P7 P8 P9 P10 P11 CR00 R/W 1 bit R/W -- 8 bits -- 16 bits -- -- -- -- -- -- -- -- -- Undefined 00H After Reset 72 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE Table 5-4. Special-Function Register List (2/3) Manipulatable Bit Unit Address FF49H FF4AH FF4CH FF4EH FF4FH FF60H FF61H FF62H FF63H FF70H FF71H FF72H FF73H FF74H Special-Function Register (SFR) Name 8-bit timer mode control register Watch timer mode control register Capture/compare control register 0 16-bit timer output control register 8-bit timer output control register Serial operating mode register 0 Serial bus interface control register Slave address register Interrupt timing specify register Asynchronous serial interface mode register Asynchronous serial interface status register Serial operating mode register 2 Baud rate generator control register Transmit shift register Receive buffer register FF80H FF84H FFB0H FFB2H FFB8H FFE0H FFE1H FFE2H FFE4H FFE5H FFE6H FFE8H FFE9H FFEAH FFECH FFEDH FFF0H FFF2H FFF3H A/D converter mode register A/D converter input select register LCD display mode register LCD display control register Key return mode register Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Priority order specify flag register 0L Priority order specify flag register 0H Priority order specify flag register 1L External interrupt mode register 0 External interrupt mode register 1 Memory size switching register Oscillation mode selection register Pull-up resistor option register H IF0 Symbol TMC1 TMC2 CRC0 TOC0 TOC1 CSIM0 SBIC SVA SINT ASIM ASIS CSIM2 BRGC TXS RXB ADM ADIS LCDM LCDC KRM IF0L IF0H IF1L MK0 MK0L MK0H MK1L PR0 PR0L PR0H PR1L INTM0 INTM1 IMS OSMS PUOH W R/W SIO2 W R R/W -- -- -- -- -- -- -- -- -- -- -- (Note) R/W 1 bit R/W -- R RW -- -- 8 bits 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- After Reset 00H 04H 00H Undefined 00H FFH -- -- -- -- -- 01H 00H 02H 00H -- FFH -- 00H 00H User's Manual U10105EJ4V1UM00 73 CHAPTER 5 CPU ARCHITECTURE Table 5-4. Special-Function Register List (3/3) Manipulatable Bit Unit Address FFF7H FFF9H FFFAH FFFBH Special-Function Register (SFR) Name Pull-up resistor option register L Watchdog timer mode register Oscillation stabilization time select register Processor clock control register Symbol PUOL WDTM OSTS PCC R/W 1 bit R/W -- 8 bits 16 bits -- -- -- -- 04H 00H After Reset Note The value after reset depends on products. PD78062, 78062Y: 44H, PD78063, 78063Y: C6H, PD78064, 78064Y: C8H, PD78P064, 78P064Y: C8H. 74 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing. (For details of instructions, refer to 78K/0 USER'S MANUAL: Instruction (IEU-1372). 5.3.1 Relative Addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 8 7 S jdisp8 15 PC 0 6 0 0 ... PC indicates the start address of the instruction after the BR instruction. When S = 0, all bits of are 0. When S = 1, all bits of are 1. User's Manual U10105EJ4V1UM00 75 CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 In the case of CALLF !addr11 instruction 76 fa10-8 fa7-0 4 3 CALLF 0 15 PC 0 0 0 0 11 10 1 87 0 76 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. [Illustration] 7 Operation Code 1 6 1 5 ta4-0 1 0 1 15 Effective Address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective Address+1 High Addr. 15 PC 8 7 0 User's Manual U10105EJ4V1UM00 77 CHAPTER 5 CPU ARCHITECTURE 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 78 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically addressed. Of the PD78064 and 78064Y subseries instruction words, the following instructions employ implied addressing. Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to be Specified by Implied Addressing A register for multiplicand and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values which become decimal correction targets A register for storage of digit data which undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. User's Manual U10105EJ4V1UM00 79 CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] The general register to be specified is accessed as an operand with the register specify code (Rn and RPn) of an instruction word in the registered bank specified with the register bank select flag (RBS0 to RBS1). Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL 'r' and 'rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute names (R0 to R7 and RP0 to RP3). [Description example] MOV A, C; when selecting C register as r Operation code INCW DE; when selecting DE register pair as rp Operation code 10000100 01100010 80 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE00H; when setting !addr16 to FE00H Operation code 10001110 00000000 11111110 User's Manual U10105EJ4V1UM00 81 CHAPTER 5 CPU ARCHITECTURE 5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. If the SFR area (FF00H to FF1FH) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. [Operand format] Identifier saddr saddrp Description Label of FE20H to FF1FH immediate data Label of FE20H to FF1FH immediate data (even address only) 82 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE [Description example] MOV FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 00010001 00110000 01010000 [Illustration] 7 OP code saddr-offset 0 Short Direct Memory 15 Effective Address 1 1 1 1 1 1 1 87 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 User's Manual U10105EJ4V1UM00 83 CHAPTER 5 CPU ARCHITECTURE 5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier sfr sfrp Description Special-function register name 16-bit manipulatable special-function register name (even address only) [Description example] MOV PM0, A; when selecting PM0 as sfr Operation code 11110110 00100000 [Illustration] 7 OP code sfr-offset 0 SFR 15 Effective Address 1 1 1 1 1 1 1 87 1 0 84 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.4.6 Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory to be manipulated. This addressing can be carried out for all the memory spaces. [Operand format] Identifier -- [DE], [HL] Description [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code [Illustration] 16 DE D 87 E 0 10000101 7 0 7 A 0 User's Manual U10105EJ4V1UM00 85 CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier -- [HL + byte] Description [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 10101110 00010000 86 User's Manual U10105EJ4V1UM00 CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier -- [HL + B], [HL + C] Description [Description example] In the case of MOV A, [HL + B] Operation code 5.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only. [Description example] In the case of PUSH DE Operation code 10110101 10101011 User's Manual U10105EJ4V1UM00 87 MEMO 88 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The PD78064 and 78064Y subseries units incorporate two input ports and 55 input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins. Figure 6-1. Port Types P80 P00 Port 8 P05 P87 P90 P07 P10 Port 0 Port 9 Port 1 P97 P100 Port 10 P103 P110 P17 P25 Port 2 P27 P30 Port 3 Port 11 P37 P117 P70 Port 7 P72 User's Manual U10105EJ4V1UM00 89 CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions (PD78064 subseries) Pin Name P00 P01 P02 P03 P04 P05 P07 P10 to P17 Port 1. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P70 P71 P72 P80 to P87 Port 7. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Port 8. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. This port can be used as a segment signal output port or an I/O port in 2-bit units by setting LCD control register. P90 to P97 Port 9. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. This port can be used as a segment signal output port or an I/O port in 2-bit units by setting LCD control register. P100 to P103 Port 10. 4-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. This port can directly drive LEDs. P110 to P117 Port 11. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Falling edge detection is possible. -- -- S31-S24 Port 2. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Port 3. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. SI0/SB0 SO0/SB1 SCK0 TO0 TO1 TO2 TI1 TI2 PCL BUZ -- SI2/RxD SO2/TxD SCK2/ASCK S39-S32 Input only Port 0. 7-bit input/output port. Function Input only Input/output mode can be specified bitwise. If used as an input port, a pull-up resistor can be connected by software. Dual-Function Pin INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7 90 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions (PD78064Y subseries) Pin Name P00 P01 P02 P03 P04 P05 P07 P10 to P17 Port 1. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P70 P71 P72 P80 to P87 Port 7. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Port 8. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. This port can be used as a segment signal output port or an I/O port in 2-bit units by setting LCD control register. P90 to P97 Port 9. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. This port can be used as a segment signal output port or an I/O port in 2-bit units by setting LCD control register. P100 to P103 Port 10. 4-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. This port can directly drive LEDs. P110 to P117 Port 11. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Falling edge detection is possible. -- -- S31-S24 Port 2. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. Port 3. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, a pull-up resistor can be connected by software. SI0/SB0 SO0/SB1 SCK0 TO0 TO1 TO2 TI1 TI2 PCL BUZ -- SI2/RxD SO2/TxD SCK2/ASCK S39-S32 Input only Port 0. 7-bit input/output port. Function Input only Input/output mode can be specified bitwise. If used as an input port, a pull-up resistor can be connected by software. Dual-Function Pin INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7 User's Manual U10105EJ4V1UM00 91 CHAPTER 6 PORT FUNCTIONS 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Control register Configuration Port mode register (PMm: m = 0 to 3, 7 to 11) Pull-up resistor option register (PUOH, PUOL) Key return mode register (KRM) Port Pull-up resistor Total: 57 ports (2 inputs, 55 inputs/outputs) Total: 55 (software specifiable: 55) 6.2.1 Port 0 Port 0 is an 7-bit input/output port with output latch. P01 to P05 pins can specify the input mode/output mode in 1-bit units with the port mode register 0. P00 and P07 pins are input-only ports. When P01 to P05 pins are used as input ports, a pull-up resistor can be connected to them in 5-bit units with a pull-up resistor option register L. Dual-functions include external interrupt input, external count clock input to the timer and crystal connection for subsystem clock oscillation. RESET input sets port 0 to input mode. Figures 6-2 and 6-3 show block diagrams of port0. Caution Because port 0 also serves for external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1. 92 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS Figure 6-2. P00 and P07 Configurations RD Internal bus P00/INTP0/TI00, P07/XT1 Figure 6-3. P01 to P05 Configurations VDD WRPUO PUO0 RD P-ch Selector Internal bus WRPORT Output Latch (P01 to P05) P01/INTP1/TI01. P02/INTP2 P05/INTP5 WRPM PM01-PM05 PUO : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal User's Manual U10105EJ4V1UM00 93 CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1. When P10 to P17 pins are used as input ports, a pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L. Dual-functions include an A/D converter analog input. RESET input sets port 1 to input mode. Figure 6-4 shows a block diagram of port 1. Caution A pull-up resistor cannot be used for pins used as A/D converter analog input. Figure 6-4. P10 to P17 Configurations VDD WRPUO PUO1 RD P-ch Selector Internal bus WRPORT Output Latch (P10 to P17) P10/ANI0, P17/ANI7 WRPM PM10-PM17 PUO : Pull-up resistor option register PM : Port mode register RD : Port 1 read signal WR : Port 1 write signal 94 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS 6.2.3 Port 2 (PD78064 Subseries) Port 2 is an 3-bit input/output port with output latch. P25 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2. When P25 to P27 pins are used as input ports, a pull-up resistor can be connected to them in 3-bit units with a pull-up resistor option register L. Dual-functions include serial interface data input/output and clock input/output. RESET input sets port 2 to input mode. Figures 6-5 and 6-6 show a block diagram of port 2. Cautions 1. When used as a serial interface, set the input/output and output latch according to its functions. For the setting method, refer to Figure 15-4 Serial Operating Mode Register 0 Format. 2. When reading the pin state in SBI mode, set PM2n to 1 (n = 5, 6) (Refer to the description of (10) SBI mode precautions (e) in section 15.4.3 "SBI Mode Operation"). Figure 6-5. P25, P26 Configurations (PD78064 subseries) VDD WRPUO PUO2 RD P-ch Selector Internal bus WRPORT Output Latch (P25, P26) P25/SI0/SB0, P26/SO0/SB1 WRPM PM25, PM26 Alternate Function PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal User's Manual U10105EJ4V1UM00 95 CHAPTER 6 PORT FUNCTIONS Figure 6-6. P27 Configuration (PD78064 subseries) VDD WRPUO PUO2 RD P-ch Selector Internal bus WRPORT Output Latch (P27) P27/SCK0 WRPM PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal 96 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS 6.2.4 Port 2 (PD78064Y Subseries) Port 2 is an 3-bit input/output port with output latch. P25 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2. When P25 to P27 pins are used as input ports, a pull-up resistor can be connected to them in 3-bit units with a pull-up resistor option register L. Dual-functions include serial interface data input/output and clock input/output. RESET input sets port 2 to input mode. Figures 6-7 and 6-8 show a block diagram of port 2. Caution When used as a serial interface, set the input/output and output latch according to its functions. For the setting method, refer to Figure 16-4 Serial Operating Mode Register 0 Format. Figure 6-7. P25, P26 Configurations (PD78064Y subseries) VDD WRPUO PUO2 RD P-ch Selector Internal bus WRPORT Output Latch (P25, P26) P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 WRPM PM25, PM26 Alternate Function PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal User's Manual U10105EJ4V1UM00 97 CHAPTER 6 PORT FUNCTIONS Figure 6-8. P27 Configuration (PD78064Y subseries) VDD WRPUO PUO2 RD P-ch Selector Internal bus WRPORT Output Latch (P27) P27/SCK0/SCL WRPM PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal 98 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS 6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3. When P30 to P37 pins are used as input ports, a pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register L. Dual-functions include timer input/output, clock output and buzzer output. RESET input sets port 3 to input mode. Figure 6-9 shows a block diagram of port 3. Figure 6-9. P30 to P37 Configurations VDD WRPUO PUO3 RD P-ch Selector Internal bus WRPORT Output Latch (P30 to P37) P30/TO0 P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37 WRPM PM30-PM37 Alternate Function PUO : Pull-up resistor option register PM : Port mode register RD : Port 3 read signal WR : Port 3 write signal User's Manual U10105EJ4V1UM00 99 CHAPTER 6 PORT FUNCTIONS 6.2.6 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7. When pins P70 to P72 are used as input port pins, a pull-up resistor can be connected as a 3-bit unit by means of pull-up resistor option register L. Dual-functions include serial interface channel 2 data input/output and clock input/output. RESET input sets the input mode. Port 7 block diagrams are shown in Figures 6-10 and 6-11. Caution When used as a serial interface, set the input/output and output latch according to its functions. For the setting method, refer to Table 17-2 Serial Interface Channel 2 Operating Mode Setting. Figure 6-10. P70 Configuration VDD WRPUO PUO7 RD P-ch Selector Internal bus WRPORT Output Latch (P70) P70/SI2/RxD WRPM PM70 PUO : Pull-up resistor option register PM : Port mode register RD : Port 7 read signal WR : Port 7 write signal 100 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS Figure 6-11. P71 and P72 Configurations VDD WRPUO PUO7 RD P-ch Selector Internal bus WRPORT Output Latch (P71 and P72) P71/SO2/TxD, P72/SCK2/ASCK WRPM PM71, PM72 Alternate Function PUO : Pull-up resistor option register PM : Port mode register RD : Port 7 read signal WR : Port 7 write signal User's Manual U10105EJ4V1UM00 101 CHAPTER 6 PORT FUNCTIONS 6.2.7 Port 8 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 8. When pins P80 to P87 are used as input port pins, a pull-up resistor can be connected as an 8-bit unit by means of pull-up resistor option register H. These pins are dual-function pins and serve as LCD controller/driver segment signal outputs. RESET input sets the input mode. The port 8 block diagram is shown in Figure 6-12. Figure 6-12. P80 to P87 Configurations VDD WRPUO PUO8 RD P-ch Selector Internal bus WRPORT Output Latch (P80 to P87) P80/S39 P87/S32 WRPM PM80 to PM87 PUO : Pull-up resistor option register PM : Port mode register RD : Port 8 read signal WR : Port 8 write signal 102 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 9 This is a 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 9. When pins P90 and P97 are used as input port pins, a pull-up resistor can be connected as a 8-bit unit by means of pull-up resistor option register H. These pins are dual-function pins and serve as LCD controller/driver segment signal outputs. RESET input sets the input mode. The port 9 block diagram is shown in Figure 6-13. Figure 6-13. P90 to P97 Configurations VDD WRPUO PUO9 RD P-ch Selector Internal bus WRPORT Output Latch (P90 and P97) P90/S31 P97/S24 WRPM PM90, PM97 PUO : Pull-up resistor option register PM : Port mode register RD : Port 9 read signal WR : Port 9 write signal User's Manual U10105EJ4V1UM00 103 CHAPTER 6 PORT FUNCTIONS 6.2.9 Port 10 This is a 4-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 10. When pins P100 and P103 are used as input port pins, a pull-up resistor can be connected as a 4-bit unit by means of pull-up resistor option register H. RESET input sets the input mode. The port 10 block diagram is shown in Figure 6-14. Figure 6-14. P100 to P103 Configurations VDD WRPUO PUO10 RD P-ch Selector Internal bus WRPORT Output Latch (P100 to P103) P100-P103 WRPM PM100 to PM103 PUO : Pull-up resistor option register PM : Port mode register RD : Port 9 read signal WR : Port 9 write signal 104 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS 6.2.10 Port 11 Port 11 is an 8-bit input/output port with output latches. P110 to P117 pins can specify the input mode/output mode in 8-bit units with the port mode register 11. When they are used as input ports, a pull-up resistor can be connected to them in 8-bit units with pull-up resistor option register H. The test input flag (KRIF) can be set to 1 by detecting falling edges. Dual-functions include address/data bus function in external memory expansion mode. RESET input sets port 11 to input mode. Figures 6-15 and 6-16 show the block diagrams of port 4 and falling edge detection circuit, respectively. Figure 6-15. P40 to P47 Configurations VDD WRPUO PUO11 RD P-ch Selector Internal bus WRPORT Output Latch (P110 to P117) P110-P117 WRPM PM110 to PM117 PUO : Pull-up resistor option register MM : Memory expansion mode register RD : Port 4 read signal WR : Port 4 write signal Figure 6-16. Block Diagram of Falling Edge Detection Circuit P110 P111 P112 P113 P114 P115 P116 P117 KRMK Standby release signal Falling edge detection circuit KRIF setting signal User's Manual U10105EJ4V1UM00 105 CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following three types of registers control the ports. * Port mode registers (PM0 to PM3, PM7 to PM11) * Pull-up resistor option register (PUOH, PUOL) * Key return mode register (KRM) (1) Port mode registers (PM0 to PM3, PM7 to PM11) These registers are used to set port input/output in 1-bit units. PM0 to PM3 and PM7 to PM11 are independently set with a 1-bit or 8-bit memory manipulation instruction RESET input sets registers to FFH. When port pins are used as the dual-function pins, set the port mode register and output latch according to Table 6-4. Cautions 1. Pins P00 and P07 are input-only pins. 2. As port 0 has a dual function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 106 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS Table 6-4. Port Mode Register and Output Latch Settings when Using Dual-Functions Pin Name Dual-functions Name P00 INTP0 TI00 P01 INTP1 TI01 P02 to P05 P07Note1 P10 to P17Note1 Input/Output PMxx Pxx Input Input Input Input Input Input Input Output Input Output Output Output Output 1 (Fixed) 1 (Fixed) 1 1 1 1 (Fixed) 1 0 1 0 0 xNote2 xNote2 None None x x x None x 0 x 0 0 INTP2 to INTP5 XT1 ANI0 to ANI7 TO0 to TO2 TI1, TI2 PCL BUZ S39 to S32 S31 to S24 P30 to P32 P33, P34 P35 P36 P80 to P87 P90 to P97 Notes 1. If these ports are read out when these pins are used in the alternative function mode, undefined values are read. 2. When the P80 to P87 and P90 to P97 pins are used for dual functions, set the function by the LCD display control register. Caution When port 2 and port 7 are used for serial interface, the I/O latch or output latch must be set according to its function. For the setting methods, see Figure 15-4 "Serial Operation Mode Register 0 Format," Figure 16-4 "Serial Operation Mode Register 0 Format," and Table 17-2 "Serial Interface Channel 2 Operating Mode Settings." Remarks x Pxx : don't care : port output latch PMxx : port mode register User's Manual U10105EJ4V1UM00 107 CHAPTER 6 PORT FUNCTIONS Figure 6-17. Port Mode Register Format Symbol PM0 7 1 6 1 5 4 3 2 1 0 1 Address FF20H After Reset FFH R/W R/W PM05 PM04 PM03 PM02 PM01 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W * PM2 PM27 PM26 PM25 1 1 1 1 1 FF22H FFH R/W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R/W PM7 1 1 1 1 1 PM72 PM71 PM70 FF27H FFH R/W PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 FF28H FFH R/W PM9 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 FF29H FFH R/W PM10 1 1 1 1 PM103 PM102 PM101 PM100 FF2AH FFH R/W PM11 PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110 FF2BH FFH R/W PMmn 0 1 Pmn Pin Input/Output Mode Selection (m = 0-3, 7-11 : n = 0-7) Output mode (output buffer ON) Input mode (output buffer OFF) 108 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where pull-up resistor use has been specified with PUOH, PUOL. No pull-up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin, irrespective of PUOH or PUOL setting. PUOH and PUOL are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor. 2. When ports 1, 8, and 9 are used as dual-function pins, a pull-up resistor cannot be used even if 1 is set in PUOm (m = 1, 8, 9). Figure 6-18. Pull-Up Resistor Option Register Format After Reset 00H Symbol PUOH 7 0 7 6 0 6 0 5 0 5 0 4 0 4 0 3 2 1 0 Address FFF3H R/W R/W PUO11 PUO10 PUO9 PUO8 3 2 1 0 PUOL PUO7 PUO3 PUO2 PUO1 PUO0 FFF7H 00H R/W PUOm 0 1 Pm Internal Pull-up Resistor Selection (m = 0-3, 7-11) Internal pull-up resistor not used Internal pull-up resistor used Caution Zeros must be set to bits 4 to 7 of PUOH and bit 4 to 6 of PUOL. User's Manual U10105EJ4V1UM00 109 CHAPTER 6 PORT FUNCTIONS (3) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 11), and selects the port 11 falling edge input. KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-19. Key Return Mode Register Format Symbol KRM 7 0 6 0 5 0 4 0 3 2 1 0 Address FFB8H After Reset 02H R/W R/W KRM3 KRM2 KRMK KRIF KRIF 0 1 Key Return Signal Detection Flag Not Detected Detected (Falling edge detection of port 11) KRMK Standby Mode Control by Key Return Signal 0 1 Standby mode release enabled Standby mode release disabled KRM3 KRM2 Selection of Port 11 Falling Edge Input 0 0 1 1 0 1 0 1 P117 P114-P117 P112-P117 P110-P117 Caution When falling edge detection of port 11 is used, KRIF should be cleared to 0 (not cleared to 0 automatically). 110 User's Manual U10105EJ4V1UM00 CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 6.4.2 Reading from input/output port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. User's Manual U10105EJ4V1UM00 111 [MEMO] 112 User's Manual U10105EJ4V1UM00 CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register. (2) Subsystem clock oscillator The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock oscillator is not used, not using the internal feedback resistance can be set by the processor clock control register. This enables to decrease power consumption in the STOP mode. 7.2 Clock Generator Configuration The clock generator consists of the following hardware. Table 7-1. Clock Generator Configuration Item Control register Oscillation mode selection register (OSMS) Main system clock oscillator Oscillator Subsystem clock oscillator Configuration Processor clock control register (PCC) User's Manual U10105EJ4V1UM00 113 CHAPTER 7 CLOCK GENERATOR Figure 7-1. Block Diagram of Clock Generator FRC XT1/P07 XT2 Subsystem Clock Oscillator Main System Clock Oscillator fXT Prescaler Selector Watch Timer, Clock Output Function Clock to Peripheral Hardware X1 X2 fX Scaler 1/2 Prescaler fXX fXX 4 fXX 23 2 fXX 22 fXX 2 fXT 2 Selector fX 2 Standby Control Circuit 3 CPU Clock (fCPU) To INTP0 Sampling Clock STOP MCS MCC FRC CLS CSS PCC2 PCC1 PCC0 Oscillation Mode Selection Register Internal Bus Processor Clock Control Register 114 User's Manual U10105EJ4V1UM00 CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: * Processor clock control register (PCC) * Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor. The PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the PCC to 04H. Figure 7-2. Subsystem Clock Feedback Resistor FRC P-ch Feedback resistor XT1 XT2 User's Manual U10105EJ4V1UM00 115 CHAPTER 7 CLOCK GENERATOR Figure 7-3. Processor Clock Control Register Format Symbol PCC 7 MCC 6 FRC 5 CLS 4 CSS 3 0 2 1 0 Address FFFBH After Reset 04H R/W R/W Note 1 PCC2 PCC1 PCC0 R/W CSS PCC2 PCC1 PCC0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 CPU CIock Selection (fCPU) MCS=1 fXX fXX/2 fXX/2 fXX/2 fXX/2 2 3 4 MCS=0 fx /2 (0.8 s) fx/2 (1.6 s) 2 fx (0.4 s) fx/2 (0.8 s) fx/22(1.6 s) fx/2 (3.2 s) 3 4 0 0 0 1 0 0 fx/23(3.2 s) fx/24(6.4 s) fx/2 (12.8 s) 5 fx/2 (6.4 s) 1 0 0 1 fXT/2 (122 s) Other than above Setting prohibited R CLS 0 1 CPU Clock Status Main system clock Subsystem clock R/W FRC 0 1 Subsystem Clock Feedback Resistor Selection Internal feedback resistor used Internal feedback resistor not used R/W MCC 0 1 Main System Clock Oscillation Control Oscillation possible Oscillation stopped Note 2 Notes 1. Bit 5 is Read Only. 2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock oscillation. A STOP instruction should not be used. Caution Bit 3 must be set to 0. Remarks 1. fXX 2. fX 3. fXT : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency : Subsystem clock oscillation frequency 4. MCS : Bit 0 of oscillation mode selection register 5. Figures in parentheses indicate minimum instruction execution time : 2fCPU when operating at fX = 5.0 MHz or fXT = 32.768 kHz. 116 User's Manual U10105EJ4V1UM00 CHAPTER 7 CLOCK GENERATOR (2) Oscillation mode selection register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock. OSMS is set with 8-bit memory manipulation instruction. RESET input sets OSMS to 00H. Figure 7-4. Oscillation Mode Selection Register Format After Reset 00H Symbol OSMS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MCS Address FFF2H R/W W MCS 0 1 Main System Clock Scaler Control Scaler used Scaler not used Cautions 1. Writing to OSMS should be performed only immediately after reset signal release and before peripheral hardware operation starts. As shown in Figure 7-5 below, writing data (including same data as previous) to OSMS cause delay of main system clock cycle up to 2/fx during the write operation. Therefore, if this register is written during the operation, in peripheral hardware which operates with the main system clock, a temporary error occurs in the count clock cycle of timer, etc. In addition, because the oscillation mode is changed by this register, the clocks for peripheral hardware as well as that for the CPU are switched. 2. When writing "1" to MCS, VDD must be 2.7 V or higher before the write execution. Figure 7-5. Main System Clock Waveform due to Writing to OSMS Write to OSMS (MCS 0) Max. 2/fX fXX * Operating at fXX = fX/2 (MCS = 0) Operating at fXX = fX/2 (MCS = 0) Remark fxx : Main system clock frequency (fx or fx/2) fx : Main system clock oscillation frequency User's Manual U10105EJ4V1UM00 117 CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin. Figure 7-6 shows an external circuit of the main system clock oscillator. Figure 7-6. External Circuit of Main System Clock Oscillator (a) Crystal and ceramic oscillation (b) External clock IC X2 External Clock PD74HCU04 X2 X1 X1 Crystal or Ceramic Resonator * Caution Do not execute the STOP instruction or do not set MCC to 1 if an external clock is used. This is because the X2 pin is connected to VDD via a pull-up resistor. 118 User's Manual U10105EJ4V1UM00 CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin. Figure 7-7 shows an external circuit of the subsystem clock oscillator. Figure 7-7. External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation IC XT1 External Clock (b) External clock XT1 32.768 kHz XT2 PD74HCU04 XT2 Cautions 1. When using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in Figures 7-6 and 7-7 to prevent any effects from wiring capacities. q q Minimize the wiring length. Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. Do not fetch signals from the oscillator. q q Take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. Figure 7-8 shows examples of oscillator having bad connection. Figure 7-8. Examples of Oscillator with Bad Connection (1/2) (a) Wiring of connection circuits is too long (b) Signal conductors intersect each other PORTn (n=0-3, 7-11) IC X2 X1 IC X2 X1 Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2. User's Manual U10105EJ4V1UM00 119 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Oscillator with Bad Connection (2/2) (c) Changing high current is too near a signal conductor (d) Current flows through the grounding line of the oscillator (potential at points A, B, and C fluctuate) VDD Pnm IC X2 X1 IC X2 X1 High Current A B High Current C (e) Signals are fetched (f) Signal conductors of the main and sub system clocks are parallel and near each other IC X2 X1 IC X2 X1 XT1 XT2 XT1 and X1 are wiring in parallel Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Cautions 2. In Figure 7-8 (f), XT1 and X1 are wired in parallel. Thus, the cross-talk noise of X1 may increase with XT1, resulting in malfunctioning. To prevent that from occurring, it is recommended to wire XT1 and X1 so that they are not in parallel. 120 User's Manual U10105EJ4V1UM00 CHAPTER 7 CLOCK GENERATOR 7.4.3 Scaler The scaler divides the main system clock oscillator output (fXX) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. * XT1 : Connect to VDD XT2 : Open In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. To minimize leakage current, the above internal feedback resistance can be removed with bit 6 (FRC) of the processor clock control register. In this case also, connect the XT1 and XT2 pins as described above. User's Manual U10105EJ4V1UM00 121 CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. * Main system clock * Subsystem clock * CPU clock fCPU fXX fXT * Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC) and the oscillation mode selection register (OSMS). (a) Upon generation of RESET signal, the lowest speed mode of the main system clock (12.8 s when operated at 5.0 MHz) is selected (PCC = 04H, OSMS = 00H). Main system clock oscillation stops while low level is applied to RESET pin. (b) With the main system clock selected, one of the six CPU clock types (0.4s. 0.8s, 1.6s, 3.2s, 6.4s, 12.8s @ 5.0 MHz) can be selected by setting the PCC and OSMS. (c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. To decrease current consumption in the STOP mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock. (d) The PCC can be used to select the subsystem clock and to operate the system with low current consumption (122 s when operated at 32.768 kHz). (e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT mode can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.) (f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to 16-bit timer/event counter, the watch timer, and clock output functions only. Thus, 16-bit timer/event counter (when selecting watch timer output for count clock operating with subsystem clock), the watch function, and the clock output function can also be continued in the standby state. However, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped. (Except external input clock operation) 122 User's Manual U10105EJ4V1UM00 CHAPTER 7 CLOCK GENERATOR 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the instruction execution time can be changed by bit 0 to bit 2 (PCC0 to PCC2) of the PCC. (b) If bit 7 (MCC) of the PCC is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. When bit 4 (CSS) of the PCC is set to 1 and the operation is switched to subsystem clock operation (CLS = 1) after that, the main system clock oscillation stops (see Figure 7-9). Figure 7-9. Main System Clock Stop Function (1/2) (a) Operation when MCC is set after setting CSS with main system clock operation MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock (b) Operation when MCC is set in case of main system clock operation MCC CSS CLS L L Oscillation does not stop. Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock User's Manual U10105EJ4V1UM00 123 CHAPTER 7 CLOCK GENERATOR Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The instruction execution time remains constant (122 s when operated at 32.768 kHz) irrespective of bit 0 to bit 2 (PCC0 to PCC2) of the PCC. (b) Watchdog timer counting stops. Caution Do not execute the STOP instruction while the subsystem clock is in operation. 124 User's Manual U10105EJ4V1UM00 CHAPTER 7 CLOCK GENERATOR 7.6 Changing System Clock and CPU Clock Settings 7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the pre-switchover clock for several instructions (see Table 7-2). Determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (CLS) of the PCC register. Table 7-2. Maximum Time Required for CPU Clock Switchover Set Values after Switchover Set Values before Switchover MCS CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 X 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 X X X 8 instructions 4 instructions 2 instructions 1 instruction 1 instruction 0 0 1 16 instructions 4 instructions 2 instructions 1 instruction 1 instruction 0 1 0 16 instructions 8 instructions 2 instructions 1 instruction 1 instruction 0 1 1 16 instructions 8 instructions 4 instructions 1 instruction 1 instruction 1 0 0 16 instructions 8 instructions 4 instructions 2 instructions 1 instruction 1 1 X X X fX/2fXT instruction fX/4fXT instruction fX/8fXT instruction fX/16fXT instruction fX/32fXT instruction (77 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions) 0 fX/4fXT instruction fX/8fXT instruction fX/16fXT instruction fX/32fXT instruction fX/64fXT instruction (39 instructions) (20 instructions) (10 instructions) (5 instructions) (3 instructions) Caution Selection of the CPU clock cycle scaling factor (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be performed simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle scaling factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0). Remarks 1. One instruction is the minimum instruction execution time with the pre-switchover CPU clock. 2. Figures in parentheses apply to operation with fX = 5.0 MHz and fXT = 32.768 kHz. User's Manual U10105EJ4V1UM00 125 CHAPTER 7 CLOCK GENERATOR 7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching VDD RESET Interrupt Request Signal System Clock CPU Clock fXX fXX fXT Subsystem Clock Operation fXX High-Speed Operation Minimum Maximum Speed Operation Speed Operation Wait (26.2 ms : 5.0 MHz) Internal Reset Operation (1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation stabilization time (217/fX) is secured automatically. After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8 s when operated at 5.0 MHz). (2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds, the PCC and OSMS are rewritten and the maximum-speed operation is carried out. (3) Upon detection of a decrease of the VDD voltage due to an interrupt, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). (4) Upon detection of VDD voltage reset due to an interrupt, 0 is set to the MCC and oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation, the PCC and OSMS are rewritten and the maximum-speed operation is resumed. Caution When subsystem clock is being operated while main system clock was stopped, if switching to the main system clock is made again, be sure to switch after securing oscillation stable time by software. 126 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER The timers incorporated into the PD78064 and 78064Y subseries are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency or one-shot pulse output. (2) 8-bit timers/event counters 1 and 2 (TM1 and TM2) TM1 and TM2 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency. Two 8-bit timer/event counters can be used as one 16-bit timer/event counter (See CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2). (3) Watch timer (TM3) This timer can set a flag every 0.5 sec. and simultaneously generates interrupts at the preset time intervals (See CHAPTER 10 WATCH TIMER). (4) Watchdog timer (WDTM) WDTM can perform the watchdog timer function or generate non-maskable interrupts, maskable interrupts and RESET at the preset time intervals (See CHAPTER 11 WATCHDOG TIMER). (5) Clock output control circuit This circuit supplies other devices with the divided main system clock and the subsystem clock (See CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT). (6) Buzzer output control circuit This circuit outputs the buzzer frequency obtained by dividing the main system clock (See CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT). User's Manual U10105EJ4V1UM00 127 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Types and Functions 16-bit Timer/ event Counter 8-bit Timer/event Counters 1 and 2 Watch Timer Watchdog Timer Type Interval timer External event counter Timer output PWM output 2 channelsNote1 -- 2 channels -- -- -- -- 1 channelNote2 -- -- -- -- -- -- 1 channelNote3 -- -- -- -- -- -- -- Function Pulse width measurement Square-wave output One-shot pulse output Interrupt request Test input Notes 1. When capture/compare registers (CR00, CR01) are specified as compare registers. 2. TM3 can perform both watch timer and interval timer functions at the same time. 3. WDTM can perform either the watchdog timer function or the interval timer function. 128 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. * Interval timer * PWM output * Pulse width measurement * External event counter * Square-wave output * One-shot pulse output (1) Interval timer TM0 generates interrupts at the preset time interval. Table 8-2. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time MCS = 1 MCS = 0 Maximum Interval Time MCS = 1 216 -- MCS = 0 MCS = 1 Resolution MCS = 0 2 x TI00 input cycle -- 2 x 1/fX (400 ns) 2 x 1/fX (400 ns) 22 x 1/fX 22 x 1/fX 216 x TI00 input cycle 216 x 1/fX TI00 input edge cycle -- 1/fX (200 ns) 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) (13.1 ms) x 1/fX 217 x 1/fX (800 ns) 23 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (1.6 s) (3.2 s) (52.4 ms) 216 (104.9 ms) (800 ns) 2 x watch timer output cycle x watch timer output cycle Watch timer output edge cycle Remarks 1. fX: Main system clock oscillation frequency 2. MCS: Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz (2) PWM output TM0 can generate 14-bit resolution PWM output. (3) Pulse width measurement TM0 can measure the pulse width of an externally input signal. (4) External event counter TM0 can measure the number of pulses of an externally input signal. User's Manual U10105EJ4V1UM00 129 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 Maximum Pulse Width MCS = 1 MCS = 0 MCS = 1 Resolution MCS = 0 2 x TI00 input cycle 2 x 1/fX -- 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 216 x TI00 input cycle 216 x 1/fX -- 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) TI00 input edge cycle 1/fX -- 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 2 x watch timer output cycle 216 x watch timer output cycle Watch timer output edge cycle Remarks 1. fX: Main system clock oscillation frequency 2. MCS: Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz (6) One-shot pulse output TM0 is able to output one-shot pulse which can set any width of output pulse. 130 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 8-4. 16-Bit Timer/Event Counter Configuration Item Timer register Register Timer output 16 bits x 1 (TM0) Capture/compare register: 16 bits x 2 (CR00, CR01) 1 (TO0) Timer clock select register 0 (TCL0) 16-bit timer mode control register (TMC0) Capture/compare control register 0 (CRC0) Control register 16-bit timer output control register (TOC0) Port mode register 3 (PM3) External interrupt mode register 0 (INTM0) Sampling clock select register (SCS) Configuration User's Manual U10105EJ4V1UM00 131 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-1. 16-Bit Timer/Event Counter Block Diagram Internal bus Capture/Compare Control Register 0 CRC02 CRC01 CRC00 INTP1 Selector TI01/ P01/INTP1 16-Bit Capture/Compare Control Register (CR00) Match Selector INTTM3 2fXX fXX fXX/2 fXX/22 TI00/P00/ INTP0 Note 1 Match 3 3 PWM Pulse Output Controller TMC01-TMC03 16-Bit Timer Register (TM0) Clear Clear Circuit INTTM00 Note 2 16-Bit Timer/Event Counter Output Control Circuit TMC01-TMC03 2 INTTM01 INTP0 TO0/P30 TCL06 TCL05 TCL04 Timer Clock Selection Register 0 CRC02 16-Bit Capture/Compare Control Register (CR01) TMC03 TMC02 TMC01 OVF0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 16-Bit Timer Output Control Register 16-Bit Timer Mode Control Register Internal Bus Notes 1. Edge detection circuit 2. The configuration of the 16-bit timer/event counter output control circuit is shown in Figure 8-2. 132 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram PWM Pulse Output Control Circuit Level Inversion CRC02 INTTM01 CRC00 INTTM00 Edge Detection Circuit Selector Selector INV S Q TO0/P30 TI00/P00/ INTP0 One-Shot Pulse Output Control Circuit R 3 2 ES11 ES10 External Interrupt Mode Register 0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 16-Bit Timer Output Control Register TMC03 TMC02 TMC01 16-Bit Timer Mode Control Register P30 Output Latch PM30 Port Mode Register 3 Internal Bus Remark The circuitry enclosed by the dotted line is the output control circuit. User's Manual U10105EJ4V1UM00 133 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0. When CR00 is used as a compare register, the value set in the CR00 is constantly compared with the 16bit timer register (TM0) count value, and an interrupt request (INTTM00) is generated if they match. It can also be used as the register which holds the interval time when TM0 is set to interval timer operation, and as the register which sets the pulse width in the PWM operating mode. When CR00 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin or the INTP1/TI01 pin as the capture trigger. Setting of the INTP0/TI00 or INTP1/TI01 valid edge is performed by means of external interrupt mode register 0. If CR00 is specified as a capture register and capture trigger is specified to be the valid edge of the INTP0/ TI00 pin, the situation is as shown in the following table. Table 8-5. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge ES11 0 0 1 1 ES10 0 1 0 1 INTP0/TI00 Pin Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges No capture operation CR00 Capture Trigger Valid Edge Rising edge Falling edge CR00 is set by a 16-bit memory manipulation instruction. After RESET input, the value of CR00 is undefined. (2) Capture/compare register 01 (CR01) CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register 0. When CR01 is used as a compare register, the value set in the CR01 is constantly compared with the 16bit timer register (TM0) count value, and an interrupt request (INTTM01) is generated if they match. When CR01 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin as the capture trigger. Setting of the INTP0/TI00 valid edge is performed by means of external interrupt mode register 0. CR01 is set with a 16-bit memory manipulation instruction. After RESET input, the value of CR01 is undefined. (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses. TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register (CR01) should first be set as a capture register. RESET input sets TM0 to 0000H. Caution As reading of the value of TM0 is performed via CR01, the previously set value of CR01 is lost. 134 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Control Registers The following seven types of registers are used to control the 16-bit timer/event counter. * Timer clock select register 0 (TCL0) * 16-bit timer mode control register (TMC0) * Capture/compare control register 0 (CRC0) * 16-bit timer output control register (TOC0) * Port mode register 3 (PM3) * External interrupt mode register 0 (INTM0) * Sampling clock select register (SCS) (1) Timer clock select register 0 (TCL0) This register is used to set the count clock of the 16-bit timer register. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TCL0 value to 00H. Remark TCL0 has the function of setting the PCL output clock in addition to that of setting the count clock of the 16-bit timer register. Cautions 1. Setting of the TI00/INTP0 pin valid edge is performed by external interrupt mode register 0, and selection of the sampling clock frequency is performed by the sampling clock selection register. 2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory manipulation instruction. 3. To read the count value when TI00 has been specified as the TM0 count clock, the value should be read from TM0, not from capture/compare register 01 (CR01). 4. When rewriting TCL0 to other data, stop the timer operation beforehand. User's Manual U10105EJ4V1UM00 135 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-3. Timer Clock Selection Register 0 Format Symbol 7 6 5 4 3 2 1 0 Address FF40H After Reset 00H R/W R/W TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 MCS=1 0 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fXT (32.768 kHz) fXX fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 2 3 4 MCS=0 fX fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 2 3 4 (5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 2 (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) 3 4 5 5 5 6 6 7 6 7 7 8 Other than above Setting prohibited 16-Bit Timer Register Count Clock Selection TCL06 TCL05 TCL04 MCS=1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TI00 (Valid edge specifiable) 2fXX fXX fXX/2 fXX/2 2 MCS=0 Setting prohibited fX fX/2 fX/2 2 fX fX/2 fX/2 fX/2 2 3 (5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (5.0 MHz) (2.5 MHz) (1.25 MHz) Watch timer output (INTTM 3) Setting prohibited Other than above CLOE 0 1 PCL Output Control Output disabled Output enabled Remarks 1. fXX 2. fX 3. fXT : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of oscillation mode selection register 7. Figures in parentheses apply to operation with fX = 5.0 MHz of fXT = 32.768 kHz. 136 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. TMC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC0 value to 00H. Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set in TMC01 to TMC03, respectively. Set 0, 0, 0 in TMC01 to TMC03 to stop the operation. User's Manual U10105EJ4V1UM00 137 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4. 16-Bit Timer Mode Control Register Format Symbol TMC0 7 0 6 0 5 0 4 0 3 2 1 0 Address FF48H After Reset 00H R/W R/W TMC03 TMC02 TMC01 OVF0 OVF0 16-Bit Timer Register Overflow Detection 0 1 Overflow not detected Overflow detected TMC03 TMC02 TMC01 Operating Mode Clear Mode Selection Operation stop (TM0 cleared to 0) PWM mode (free running) TO0 Output Timing Selection Interrupt Generation 0 0 0 No change Not Generated 0 0 1 PWM pulse output Match between TM0 and CR00 or match between TM0 and CR01 0 1 0 Free running mode 0 1 1 Match between TM0 and CR00, match between TM0 and CR01 or TI00 valid edge Match between TM0 and CR00 or match between TM0 and CR01 Generated on match between TM0 and CR00, and match between TM0 and CR01 1 0 0 Clear & start on TI00 valid edge 1 0 1 Match between TM0 and CR00, match between TM0 and CR01 or TI00 valid edge Match between TM0 and CR00 or match between TM0 and CR01 1 1 0 Clear & start on match between TM0 and CR00 1 1 1 Match between TM0 and CR00, match between TM0 and CR01 or TI00 valid edge Remark TO0 TI00 TM0 : 16-bit timer/event counter output pin : 16-bit timer/event counter input pin : 16-bit timer register CR00 : Compare register 00 CR01 : Compare register 01 Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation (by setting TMC01 to TMC03 to 0, 0, 0). 2. Set the valid edge of the TI00/INTP0 pin with an external interrupt mode register 0 and select the sampling clock frequency with a sampling clock select register. 3. When using the PWM mode, set the PWM mode and then set data to CR00. 4. If clear & start mode on match between TM0 and CR00 is selected, when the set value of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, OVF0 flag is set to 1. 138 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H. Figure 8-5. Capture/Compare Control Register 0 Format Symbol CRC0 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FF4CH After Reset 04H R/W R/W CRC02 CRC01 CRC00 CRC00 CR00 Operating Mode Selection 0 1 Operates as compare register Operates as capture register CRC01 CR00 Capture Trigger Selection 0 1 Captures on valid edge of TI01 Captures on valid edge of TI00 CRC02 CR01 Operating Mode Selection 0 1 Operates as compare register Operates as capture register Cautions 1. Timer operation must be stopped before setting CRC0. 2. When clear & start mode on a match between TM0 and CR00 is selected with the 16bit timer mode control register, CR00 should not be specified as a capture register. User's Manual U10105EJ4V1UM00 139 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip-flop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation enabling/disabling, and output trigger for a one-shop pulse by software. TOC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TOC0 value to 00H. Cautions 1. Timer operation must be stopped before setting TOC0. 2. If LVS0 and LVR0 are read after data is set, they will be 0. 3. OSPT is cleared automatically after data setting, and will therefore be 0 if read. Figure 8-6. 16-Bit Timer Output Control Register Format Symbol TOC0 7 0 6 5 4 3 2 1 0 Address FF4EH After Reset 00H R/W R/W OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 TOE0 16-Bit Timer/Event Counter Output Control 0 1 Output disabled (Port mode) Output enabled In PWM Mode TOC01 Active level selection 0 1 Active high Active low In Other Modes Timer output F/F control by match of CR00 and TM0 Inversion operation disabled Inversion operation enabled LVS0 0 0 1 1 LVR0 0 1 0 1 16-Bit Timer/Event Counter Timer Output F/F Status Setting No change Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TOC04 Timer output F/F control by match of CR01 and TM0 0 1 Inversion operation disabled Inversion operation enabled OSPE One-Shot Pulse Output Control 0 1 Continuous pulse output One-shot pulse output OSPT Control of One-Shot Pulse Output Trigger by Software 0 1 One-shot pulse trigger not used One -shot pulse trigger used 140 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH. Figure 8-7. Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0 Address FF23H After Reset FFH R/W R/W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n P3n Pin Input/Output Mode Selection (n = 0 to 7) 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) User's Manual U10105EJ4V1UM00 141 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Figure 8-8. External Interrupt Mode Register 0 Format Symbol 7 6 5 4 3 2 1 0 0 0 Address FFECH After Reset 00H R/W R/W INTM0 ES31 ES30 ES21 ES20 ES11 ES10 ES11 0 0 1 1 ES10 0 1 0 1 INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES21 0 0 1 1 ES20 0 1 0 1 INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES31 0 0 1 1 ES30 0 1 0 1 INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges 142 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Sampling clock select registers (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS value to 00H. Figure 8-9. Sampling Clock Select Register Format Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF47H After Reset 00H R/W R/W SCS1 SCS0 INTP0 Sampling Clock Selection SCS1 SCS0 MCS=1 0 0 1 1 0 1 0 1 fXX/2 fXX/2 fXX/2 fXX/2 N 7 5 7 5 8 6 MCS=0 fX/2 (39.1 kHz) fX/2 (156.3 kHz) fX/2 (78.1 kHz) 6 fX/2 (19.5 kHz) fX/2 (78.1 kHz) fX/2 (39.1 kHz) 7 6 Caution fXX/2N is the clock supplied to the CPU, and fXX/25, fXX/26, and fXX/27 are clocks supplied to peripheral hardware. fXX/2N is stopped in HALT mode. Remarks 1. N 2. fXX 3. fX : Value set in bit 0 to bit 2 (PCC0 to PCC2) of the processor clock control register (N = 0 to 4) : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency 4. MCS : Bit 0 of oscillation mode selection register 5. Figures in parentheses apply to operation with fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 143 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4 16-Bit Timer/Event Counter Operations 8.4.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupts are generated repeatedly using the count value set in 16-bit capture/compare register 00 (CR00) beforehand as the interval. When the count value of the 16-bit timer register (TM0) matches the value set to CR00, counting continues with the TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated. Count clock of the 16-bit timer/event counter can be selected with bit 4 to bit 6 (TCL04 to TCL06) of the timer clock select register 0 (TCL0). Figure 8-10. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clear & start on match TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 set as compare register Remark 0/1 : Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details. 144 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM3 2fXX fXX fXX/2 fXX/2 TI00/P00/INTP0 2 INTTM00 Selector 16-Bit Timer Register (TM0) OVF0 Clear Circuit t Figure 8-12. Interval Timer Operation Timings Count Clock TM0 Count Value 0000 0001 N 0000 0001 Clear N 0000 0001 Clear N Count Start CR00 N N N N INTTM00 Interrupt Acknowledge TO0 Interrupt Acknowledge Interval Time Interval Time Interval Time Remark Interval time = (N + 1) x t : N = 0001H to FFFFH. User's Manual U10105EJ4V1UM00 145 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time TCL06 0 0 TCL05 0 0 TCL04 0 1 MCS = 1 MCS = 0 Maximum Interval Time MCS = 1 216 MCS = 0 Resolution MCS = 1 MCS = 0 2 x TI00 input cycle Setting prohibited 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) x TI00 input cycle 216 x 1/fX (13.1 ms) TI00 input edge cycle Setting prohibited 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) Setting prohibited 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 0 1 0 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 0 1 1 1 0 0 1 1 Other than above 1 2 x watch timer output cycle Setting prohibited 216 x watch timer output cycle Watch timer output edge cycle Remarks 1. fX : Main system clock oscillation frequency 2. MCS : Bit 0 of oscillation mode selection register 3. Figures in parentheses apply to operation with fX = 5.0 MHz 8.4.2 PWM output operations Setting the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) as shown in Figure 8-13 allows operation as PWM output. Pulses with the duty rate determined by the value set in 16-bit capture/compare register 00 (CR00) beforehand are output from the TO0/ P30 pin. Set the active level width of the PWM pulse to the high-order 14 bits of CR00. Select the active level with bit 1 (TOC01) of the 16- bit timer output control register (TOC0). This PWM pulse has a 14-bit resolution. The pulse can be converted to an analog voltage by integrating it with an external low-pass filter (LPF). The PWM pulse is formed by a combination of the basic cycle determined by 28/ and the sub-cycle determined by 214/ so that the time constant of the external LPF can be shortened. Count clock can be selected with bit 4 to bit 6 (TCL04 to TCL06) of the timer clock select register 0 (TCL0). PWM output enable/disable can be selected with bit 0 (TOE0) of TOC0. Cautions 1. PWM operation mode should be selected before setting CR00. 2. Be sure to write 0 to bits 0 and 1 of CR00. 3. Do not select PWM operation mode for external clock input from the TI00/P00 pin. 146 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 0 1 0 PWM mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 set as compare register (c) 16-bit timer output control register (TOC0) OSPT TOC0 0 OSPE TOC04 LVS0 LVR0 TOC01 TOE0 x x x x x 0/1 1 TO0 Output Enabled Specifies Active Level Remarks 1. 0/1 : Setting 0 or 1 allows another function to be used simultaneously with PWM output. See the description of the respective control registers for details. 2. x : Don't care User's Manual U10105EJ4V1UM00 147 CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. capture/compare register 00 (CR00) value 216 VREF: External switching circuit reference voltage Figure 8-14. Example of D/A Converter Configuration with PWM Output PD78064, 78064Y VAN = VREF x VREF PWM signal TO0/P30 Switching Circuit Low-Pass Filter Analog Output (VAN) Figure 8-15 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner. Figure 8-15. TV Tuner Application Circuit Example +110 V PD78064, 78064Y 22 k 47 k 100 pF TO0/P30 8.2 k 8.2 k VSS GND 2SC 2352 0.22 F 0.22 F 0.22 F 47 k 47 k PC574J Electronic Tuner 148 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/ compare register 00 (CR00), respectively. Figure 8-16. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0 0 Clear & start on match of TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0 x 0 CR00 set as compare register CR01 set as compare register (c) 16-bit timer output control register (TOC0) OSPT TOC0 0 0 OSPE TOC04 LVS0 0 1 0/1 LVR0 TOC01 TOE0 0/1 1 1 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial value Inversion of output on match of TM0 and CR01 One-shot pulse output disabled Caution Values in the following range should be set in CR00 and CR01: 0000H CR01 < CR00 FFFFH Remark x : Don't care User's Manual U10105EJ4V1UM00 149 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin. (1) Pulse width measurement with free-running counter and one capture register When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-17), and the edge specified by external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set. Any of three edge specifications can be selected--rising, falling, or both edges--by means of bits 2 and 3 (ES10 and ES11) of INTM0. For valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 8-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free-Running Mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 0/1 0 CR00 set as compare register CR01 set as capture register Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 150 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter INTTM3 2fXX fXX fXX/2 fXX/2 2 Selector 16-Bit Timer Register (TM0) OVF0 TI00/P00/INTP00 16-Bit Capture/Compare Register 01 (CR01) INTP0 Internal Bus Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) t Count Clock TM0 Count Value 0000 0001 D0 D1 FFFF 0000 D2 D3 TI00 Pin Input CR01 Captured Value D0 D1 D2 D3 INTP0 OVF0 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t User's Manual U10105EJ4V1UM00 151 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin. When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set. Also, when the edge specified by bits 4 and 5 (ES20 and ES21) of INTM0 is input to the TI01/P01 pin, the value of TM0 is taken into 16-bit capture/compare register 00 (CR00) and an external interrupt request signal (INTP1) is set. Any of three edge specifications can be selected--rising, falling, or both edges--as the valid edges for the TI00/P00 pin and the TI01/P01 pin by means of bits 2 and 3 (ES10 and ES11) and bits 4 and 5 (ES20 and ES21) of INTM0, respectively. For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 8-20. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free-Running Mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 0 1 CR00 set as capture register Captured in CR00 on valid edge of TI01/P01 Pin CR01 set as capture register Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 152 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count Clock TM0 Count Value 0000 0001 D0 D1 FFFF 0000 D2 D3 TI00 Pin Input CR01 Captured Value D0 D1 D2 D3 INTP0 TI01 Pin Input CR00 Captured Value D1 INTP1 OVF0 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t (10000H - D1 + (D2 + 1)) x t User's Manual U10105EJ4V1UM00 153 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin. When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set. Also, on the inverse edge input of that of the capture operation into CR01, the value of TM0 is taken into 16-bit capture/compare register 00 (CR00). Either of two edge specifications can be selected--rising or falling--as the valid edges for the TI00/P00 pin by means of bits 2 and 3 (ES10 and ES11) of INTM0. For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Caution If the valid edge of TI00/P00 is specified to be both rising and falling edge, capture/compare register 00 (CR00) cannot perform the capture operation. Figure 8-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free-Running Mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 1 1 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 154 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count Clock TM0 Count Value 0000 0001 D0 D1 FFFF 0000 D2 D3 TI00 Pin Input CR01 Captured Value D0 D2 CR00 Captured Value D1 D3 INTP0 OVF0 (D1-D0) x t (10000H-D1 + D2) x t (D3-D2) x t User's Manual U10105EJ4V1UM00 155 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24). The edge specification can be selected from two types, rising and falling edges by INTM0 bits 2 and 3 (ES10 and ES11). In a valid edge detection, the sampling is performed by a cycle selected by the sampling clock selection register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Caution If the valid edge of TI00/P00 is specified to be both rising and falling edge, the 16-bit capture/ compare register 00 (CR00) cannot perform the capture operation. Figure 8-24. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 0 0/1 0 Clear & start with valid edge of TI00/P00 pin (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 1 1 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. Figure 8-25. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) t Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 D1 x t D0 D1 D2 0000 0001 D0 0000 0001 D1 D2 0000 0001 D2 x t 156 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated. The rising edge, the falling edge or both edges can be selected with bits 2 and 3 (ES10 and ES11) of INTM0. Because operation is carried out only after the valid edge is detected twice by sampling at the interval selected with the sampling clock select register (SCS), noise with short pulse widths can be removed. Figure 8-26. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clear & start with match of TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 set as compare register Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details. User's Manual U10105EJ4V1UM00 157 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) Clear INTTM00 TI00 Valid Edge 16-Bit Timer Register (TM0) OVF0 INTP0 16-Bit Capture/Compare Register 01 (CR01) Internal Bus Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified) TI00 Pin Input TM0 Count Value 0000 0001 0002 0003 0004 0005 N-1 N 0000 0001 0002 0003 CR00 N INTTM0 Caution When reading the external event counter count value, TM0 should be read. 158 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4.6 Square-wave output operation A square wave with any selected frequency is output at intervals of the count value preset to the 16-bit capture/ compare register 00 (CR00). The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register to 1. This enables a square wave with any selected frequency to be output. Figure 8-29. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clear & start on match of TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 set as compare register (c) 16-bit timer output control register (TOC0) OSPT TOC0 0 0 OSPE TOC04 LVS0 0 0 0/1 LVR0 TOC01 TOE0 0/1 1 1 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial value No inversion of output on match of TM0 and CR01 One-shot pulse output disabled Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details. User's Manual U10105EJ4V1UM00 159 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-30. Square-Wave Output Operation Timing TI00 Pin Input TM0 Count Value CR00 INTTM0 TO0 Pin Output 0000 0001 0002 N N-1 N 0000 0001 0002 N-1 N 0000 Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 Maximum Pulse Width MCS = 1 216 -- MCS = 0 MCS = 1 Resolution MCS = 0 2 x TI00 input cycle -- 2 x 1/fX (400 ns) 2 x 1/fX (400 ns) 22 x 1/fX 22 x 1/fX 216 x TI00 input cycle 216 x 1/fX TI00 input edge cycle -- 1/fX (200 ns) (13.1 ms) x 1/fX 217 x 1/fX 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) (800 ns) 23 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (1.6 s) (3.2 s) (52.4 ms) 216 (104.9 ms) (800 ns) 2 x watch timer output cycle x watch timer output cycle Watch timer output edge cycle Remarks 1. fX : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz 160 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4.7 One-shot pulse output operation It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin input). (1) One-shot pulse output using software trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-31, and 1 is set in bit 6 (OSPT) of TOC0 by software, a one-shot pulse is output from the TO0/P30 pin. By setting 1 in OSPT, the 16-bit timer/event counter is cleared and started, and output is activated by the count value set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter, output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (CR00). TM0 continues to operate after one-shot pulse is output. To stop TM0, 00H must be set to TMC0. Caution When outputting one-shot pulse, do not set 1 in OSPT. When outputting one-shot pulse again, execute after the INTTM00, or interrupt match signal with CR00, is generated. Figure 8-31. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0 0 Clear & start with match of TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0 0/1 0 CR00 set as compare register CR01 set as compare register (c) 16-bit timer output control register (TOC0) OSPT TOC0 0 0 OSPE TOC04 LVS0 1 1 0/1 LVR0 TOC01 TOE0 0/1 1 1 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial value Inversion of output on match of TM0 and CR01 One-shot pulse output mode Set 1 in case of output Caution Values in the following range should be set in CR00 and CR01. 0000H CR01 < CR00 FFFFH Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. See the description of the respective control registers for details. User's Manual U10105EJ4V1UM00 161 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger Set 0CH to TMC0 (TM0 count start) Count Clock TM0 Count Value CR01 Set Value CR00 Set Value OSPT INTTM01 INTTM00 TO0 Pin Output 0000 N M 0001 N N+1 N M 0000 N-1 N M N M-1 M 0000 0001 0002 N M Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively. 162 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/ P30 pin with a TI00/P00 valid edge as an external trigger. Any of three edge specifications can be selected--rising, falling, or both edges -- as the valid edges for the TI00/P00 pin by means of bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0). When a valid edge is input to the TI00/P00 pin, the 16-bit timer/event counter is cleared and started, and output is activated by the count values set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter, output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (CR00). Caution When outputting one-shot pulses, external trigger is ignored if generated again. Figure 8-33. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 0 0 0 Clear & start with valid edge of TI00/P00 pin (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0 0/1 0 CR00 set as compare register CR01 set as compare register (c) 16-bit timer output control register (TOC0) OSPT TOC0 0 0 OSPE TOC04 LVS0 1 1 0/1 LVR0 TOC01 TOE0 0/1 1 1 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial value Inversion of output on match of TM0 and CR01 One-shot pulse output mode Caution Values in the following range should be set in CR00 and CR01. 0000H CR01 < CR00 FFFFH Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. See the description of the respective control registers for details. User's Manual U10105EJ4V1UM00 163 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-34. Timing of One-Shot Pulse Output Operation Using External Trigger (With Rising Edge Specified) Set 08H to TMC0 (TM0 count start) Count Clock TM0 Count Value CR01 Set Value CR00 Set Value TI00 Pin Input INTTM01 INTTM00 TO0 Pin Output 0000 0001 N M 0000 N N+1 N M N+2 M-2 M-1 M N M M+1 M+2 M+3 N M Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively. 164 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse. Figure 8-35. 16-Bit Timer Register Start Timing Count Pulse TM0 Count Value 0000H 0001H 0002H 0003H 0004H Timer Start (2) 16-bit compare register setting Set a value other than 0000H to the 16-bit capture/compare register 00 (CR00). Thus, when using the 16-bit capture/compare register as event counter, one-pulse count operation cannot be carried out. (3) Operation after compare register change during timer count operation If the value after the 16-bit capture/compare register (CR00) is changed is smaller than that of the 16-bit timer register (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after CR00 change is smaller than that (N) before change, it is necessary to restart the timer after changing CR00. Figure 8-36. Timings After Change of Compare Register During Timer Count Operation Count Pulse CR00 N M TM0 Count Value X-1 X FFFFH 0000H 0001H 0002H Remark N>X>M User's Manual U10105EJ4V1UM00 165 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge. Figure 8-37. Capture Register Data Retention Timing Count Pulse TM0 Count Value Edge Input Interrupt Request Flag Capture Read Signal CR01 Captured Value X N+1 N N+1 N+2 M M+1 M+2 Capture Operation Ignored (5) Valid edge setting Set the valid edge of the TI00/INTP0 pin after setting bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register to 0, 0 and 0, respectively, and then stopping timer operation. Valid edge setting is carried out with bits 2 and 3 (ES10 and ES11) of the external interrupt mode register 0. (6) Re-trigger of one-shot pulse (a) One-shot pulse output using software When outputting one-shot pulse, do not set 1 in OSPT. When outputting one-shot pulse again, execute it after the INTTM00, or interrupt match signal with CR00, is generated. (b) One-shot pulse output using external trigger When outputting one-shot pulses, external trigger is ignored if generated again. 166 User's Manual U10105EJ4V1UM00 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. CR00 is set to FFFFH. When TM0 is counted up from FFFFH to 0000H. Figure 8-38. Operation Timing of OVF0 Flag Count Pulse CR00 FFFFH TM0 FFFEH FFFFH 0000H 0001H OVF0 INTTM00 User's Manual U10105EJ4V1UM00 167 [MEMO] 168 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1 8-Bit Timer/Event Counters 1 and 2 Functions For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/ event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode). 9.1.1 8-bit timer/event counter mode The 8-bit timer/event counters 1 and 2 (TM1 and TM2) have the following functions. * Interval timer * External event counter * Square-wave output User's Manual U10105EJ4V1UM00 169 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) 8-bit interval timer Interrupts are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times Minimum Interval Time MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) Remarks 1. fX MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Interval Time MCS = 1 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) MCS = 0 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) Resolution MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz. 170 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges Minimum Pulse Width MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) Remarks 1. fX MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Pulse Width MCS = 1 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) MCS = 0 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) Resolution MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 171 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupts can be generated at the preset time intervals. Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Interval Time MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) Remarks 1. fX MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Interval Time MCS = 1 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 227 x 1/fX (26.8 s) MCS = 0 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s) Resolution MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz. 172 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Pulse Width MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) Remarks 1. fX MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Pulse Width MCS = 1 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 227 x 1/fX (26.8 s) MCS = 0 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s) Resolution MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 173 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations The 8-bit timer/event counters 1 and 2 consist of the following hardware. Table 9-5. 8-Bit Timer/Event Counters 1 and 2 Configurations Item Timer register Register Timer output Configuration 8 bits x 2 (TM1, TM2) Compare register: 8 bits x 2 (CR10, CR20) 2 (TO1, TO2) Timer clock select register 1 (TCL1) Control register 8-bit timer mode control register 1 (TMC1) 8-bit timer output control register (TOC1) Port mode register 3 (PM3) 174 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-1. 8-Bit Timer/Event Counters 1 and 2 Block Diagram Internal Bus INTTM1 8-Bit Compare Register 10 (CR10) Match Match fXX/2-fXX/2 fXX/2 9 8-Bit Compare Register 20 (CR20) Note 8-Bit Timer/ Event Counter Output Control Circuit 2 4 Selector TO2/P32 Selector 11 Selector 8-Bit Timer Register 1 (TM1) TI1/P33 4 Clear 8-Bit Timer Register 2 (TM2) INTTM2 fXX/2-fXX/2 fXX/2 9 Selector 11 TI2/P34 4 8-Bit Timer/ Event Counter Output Control Circuit 1 4 Note TO1/P31 TCL TCL TCL TCL TCL TCL TCL TCL 17 16 15 14 13 12 11 10 Timer Clock Select Register 1 Clear Selector TMC TCE2 TCE1 12 8-Bit Timer Mode Control Register LVS2 LVR2 TOC TOE2 LVS1 LVR1 TOC TOE1 15 11 8-Bit Timer Output Control Register Internal Bus Note Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counter output control circuits 1 and 2, respectively. User's Manual U10105EJ4V1UM00 175 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Level F/F (LV1) LVR1 LVS1 TOC11 R Q S INV P31 Output Latch PM31 TO1/P31 INTTM1 TOE1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 Level F/F (LV2) fSCK LVR2 LVS2 TOC15 R Q S INV P32 Output Latch PM32 TO2/P32 INTTM2 TOE2 Remarks 1. The section in the broken line is an output control circuit. 2. fSCK : Serial clock frequency 176 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively). CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit memory manipulation instruction. When the compare register is used as 8-bit timer/event counter, the 00H to FFH values can be set. When the compare register is used as 16-bit timer/event counter, the 0000H to FFFFH values can be set. RESET input makes CR10 and CR20 undefined. Caution When using the compare register as 16-bit timer/event counter, be sure to set data after stopping timer operation. (2) 8-bit timer registers 1, 2 (TM1, TM2) These are 8-bit registers to count count pulses. When TM1 and TM2 are used in the 8-bit timer x 2-channel mode, they are read with an 8-bit memory manipulation instruction. When TM1 and TM2 are used as 16-bit timer x 1-channel mode, 16-bit timer (TMS) is read with a 16-bit memory manipulation instruction. RESET input sets TM1 and TM2 to 00H. User's Manual U10105EJ4V1UM00 177 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers The following four types of registers are used to control the 8-bit timer/event counter. * Timer clock select register 1 (TCL1) * 8-bit timer mode control register 1 (TMC1) * 8-bit timer output control register (TOC1) * Port mode register 3 (PM3) (1) Timer clock select register 1 (TCL1) This register sets count clocks of 8-bit timer registers 1 and 2. TCL1 is set with an 8-bit memory manipulation instruction. RESET input sets TCL1 to 00H. 178 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-4. Timer Clock Select Register 1 Format Symbol 7 6 5 4 3 2 1 0 Address FF41H After Reset 00H R/W R/W TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 8-Bit Timer Register 1 Count Clock Selection TCL13 TCL12 TCL11 TCL10 MCS=1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 TI1 falling edge TI1 rising edge fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 2 3 4 5 MCS=0 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 2 3 4 5 (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (2.4 kHz) fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 2 (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) (1.2 kHz) 3 4 5 6 6 6 7 7 8 9 11 7 8 9 11 8 9 10 12 Other than above Setting prohibited 8-Bit Timer Register 2 Count Clock Selection TCL17 TCL16 TCL15 TCL14 MCS=1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 TI2 falling edge TI2 rising edge fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 2 3 4 5 MCS=0 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 2 3 4 5 (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (2.4 kHz) fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 2 (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) (1.2 kHz) 3 4 5 6 6 6 7 7 8 9 11 7 8 9 11 8 9 10 12 Other than above Setting prohibited Caution When rewriting TCL1 to other data, stop the timer operation beforehand. Remarks 1. 2. 3. 4. 5. 6. : fXX fX : TI1 : TI2 : MCS : Figures Main system clock frequency (fX or fX/2) Main system clock oscillation frequency 8-bit timer register 1 input pin 8-bit timer register 2 input pin Oscillation mode selection register bit 0 in parentheses apply to operation with fX = 5.0 MHz User's Manual U10105EJ4V1UM00 179 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H. Figure 9-5. 8-Bit Timer Mode Control Register Format Symbol TMC1 7 0 6 0 5 0 4 0 3 0 2 1 0 TCE1 Address FF49H After Reset 00H R/W R/W TMC12 TCE2 TCE1 8-Bit Timer Register 1 Operation Control 0 1 Operation stop (TM1 clear to 0) Operation enable TCE2 8-Bit Timer Register 2 Operation Control 0 1 Operation stop (TM2 clear to 0) Operation enable TMC12 Operating Mode Selection 0 1 8-Bit timer register x 2 channel mode (TM1, TM2) 16-Bit timer register x 1 channel mode (TMS) Cautions 1. Switch the operating mode after stopping timer operation. 2. When used as 16-bit timer register, TCE1 should be used for operation enable/stop. 180 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2. TOC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TOC1 to 00H. Figure 9-6. 8-Bit Timer Output Control Register Format Symbol 7 6 5 4 3 2 1 0 Address FF4FH After Reset 00H R/W R/W TOC1 LVS2 LVR2 TOC15 TOE2 LVS1 LVR1 TOC11 TOE1 TOE1 8-Bit Timer/Event Counter 1 Outptut Control 0 1 Output disable (port mode) Output enable TOC11 8-Bit Timer/Event Counter 1 Timer Output F/F Control 0 1 Inverted operation disable Inverted operation enable LVS1 LVR1 8-Bit Timer/Event Counter 1 Timer Output F/F Status Set 0 0 1 1 0 1 0 1 Unchanged Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TOE2 8-Bit Timer/Event Counter 2 Output Control 0 1 Output disable (port mode) Output enable TOC15 8-Bit Timer/Event Counter 2 Timer Output F/F Control 0 1 Inverted operation disable Inverted operation enable LVS2 LVR2 8-Bit Timer/Event Counter 2 Timer Output F/F Status Set 0 0 1 1 0 1 0 1 Unchanged Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited Cautions 1. Be sure to set TOC1 after stopping timer operation. 2. After data setting, 0 can be read from LVS1, LVS2, LVR1 and LVR2. User's Manual U10105EJ4V1UM00 181 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 9-7. Port Mode Register 3 Format Symbol PM3 7 6 5 4 3 2 1 0 Address FF23H After Reset FFH R/W R/W PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n P3n Pin Input/Output Mode Selection (n=0 to 7) 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) 182 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupts repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20). When the count values of the 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated. Count clock of the 8-bit timer register 1 (TM1) can be selected with bits 0 to 3 (TCL10 to TCL13) of the timer clock select register 1 (TCL1). Count clock of the 8-bit timer register 2 (TM2) can be selected with bits 4 to 7 (TCL14 to TCL17) of the timer clock select register 1 (TCL1). Figure 9-8. Interval Timer Operation Timings t Count Clock TM1 Count Value 00 01 N 00 Clear 01 N 00 Clear 01 N Count Start CR10 N N N N INTTM1 Interrupt Acknowledge Interrupt Acknowledge TO1 Interval Time Interval Time Interval Time Remark Interval time = (N + 1) x t : N = 00H to FFH User's Manual U10105EJ4V1UM00 183 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time TCL13 TCL12 TCL11 TCL10 MCS = 1 0 0 0 0 0 1 0 0 1 0 1 0 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 TI1 input cycle TI1 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) 28 x TI1 input cycle 28 x TI1 input cycle 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) TI1 input edge cycle TI1 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Interval Time Resolution 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Other than above Remarks 1. fX Setting prohibited : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz. 184 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time Minimum Interval Time TCL17 TCL16 TCL15 TCL14 MCS = 1 0 0 0 0 0 1 0 0 1 0 1 0 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 TI2 input cycle TI2 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) 28 x TI2 input cycle 28 x TI2 input cycle 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) TI2 input edge cycle TI2 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Interval Time Resolution 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Other than above Remarks 1. fX Setting prohibited : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz User's Manual U10105EJ4V1UM00 185 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1) is input. Either the rising or falling edge can be selected. When the TM1 and TM2 counted values match the values of 8-bit compare registers (CR10 and CR20), TM1 and TM2 are cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated. Figure 9-9. External Event Counter Operation Timings (with Rising Edge Specified) TI1 Pin Input TM1 Count Value 00 01 02 03 04 05 N-1 N 00 01 02 03 CR10 N INTTM1 Remark N = 00H to FFH 186 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers 10 and 20 (CR10 and CR20). The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output. Table 9-8. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges Minimum Pulse Width MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) Remarks 1. fX MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Pulse Width MCS = 1 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) MCS = 0 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) Resolution MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 187 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of 8-bit timer mode control register 1 (TMC1) is set to 1 and the 16-bit timer/counter mode is selected, the overflow signal of 8-bit timer/event counter 1 (TM1) becomes a count clock of 8-bit timer/event counter 2 (TM2). When a 2-channel 8-bit timer/event counter is used in the 16-bit timer/event counter mode, the count clock is selected with bits 0 to 3 (TCL10 to TCL13) of TCL1. Count operation enable/disable is selected with bit 0 (TCE1) of TMC1. (1) Interval timer The 8-bit timer/event counter operates as interval timer which generates interrupts repeatedly at intervals of the count value preset to 2-channel 8-bit compare registers 10 and 20 (CR10 and CR20). When the 8-bit timer register 1 (TM1) and CR10 values match and the 8-bit timer register 2 (TM2) and CR20 values match, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal (INTTM2) is generated. Count clock can be selected with bits 0 to 3 (TCL10 to TCL13) of the timer clock select register 1 (TCL1). Figure 9-10. Interval Timer Operation Timing t Count Clock TMS (TM1, TM2) Count Value 0000 0001 N 0000 0001 Clear N 0000 0001 Clear N Count Start CR10, CR20 N N N N INTTM2 Interrupt Acknowledge Interrupt Acknowledge TO2 Interval Time Interval Time Interval Time Remark Interval time = (N + 1) x t : N = 0000H to FFFFH Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment. When reading the 16-bit timer (TMS) count value, use the 16-bit memory manipulation instruction. 188 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter Minimum Interval Time TCL13 TCL12 TCL11 TCL10 MCS = 1 0 0 0 0 0 1 0 0 1 0 1 0 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 TI1 input cycle TI1 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) 28 x TI1 input cycle 28 x TI1 input cycle 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 227 x 1/fX (26.8 s) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s) TI1 input edge cycle TI1 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Interval Time Resolution 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Other than above Remarks 1. fX Setting prohibited : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 189 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2-channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input. Either the rising or falling edge can be selected. When the TM1 and TM2 counted values match the values of 8-bit compare registers 10 and 20 (CR10 and CR20), TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated. Figure 9-11. External Event Counter Operation Timings (with Rising Edge Specified) TI1 Pin Input TM1, TM2 Count Value 0000 0001 0002 0003 0004 0005 N-1 N 0000 0001 0002 0003 CR10, CR20 N INTTM2 Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment. When reading the 16-bit timer (TMS) count value, use the 16-bit memory manipulation instruction. 190 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers 10 and 20 (CR10 and CR20). The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output. Table 9-10. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter Minimum Pulse Width MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) Remarks 1. fX MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Pulse Width MCS = 1 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 227 x 1/fX (26.8 s) MCS = 0 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s) Resolution MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 3. Values in parentheses when operated at fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 191 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2 (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously with the count pulse. Figure 9-12. 8-Bit Timer Registers 1 and 2 Start Timing Count Pulse TM1, TM2 Count Value 00H 01H 02H 03H 04H Timer Start (2) 8-bit compare register 10 and 20 setting The 8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H. Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be carried out. When the 8-bit compare register is used as 16-bit timer/event counter, write data to CR10 and CR20 after setting bit 0 (TCE1) of the 8-bit timer mode control register 1 to 0 and stopping timer operation. Figure 9-13. External Event Counter Operation Timing TI1, TI2, Input CR10, CR20 00H TM1, TM2 Count Value 00H 00H 00H 00H TO1, TO2 Interrupt Request Flag 192 User's Manual U10105EJ4V1UM00 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those of 8-bit timer registers 1 and 2 (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0. Thus, if the value (M) after CR10 and CR20 change is smaller than value (N) before the change, it is necessary to restart the timer after changing CR10 and CR20. Figure 9-14. Timing after Compare Register Change during Timer Count Operation Count Pulse CR10, CR20 N M TM1, TM2 Count Value X-1 X FFFFH 0000H 0001H 0002H Remark N>X>M User's Manual U10105EJ4V1UM00 193 [MEMO] 194 User's Manual U10105EJ4V1UM00 CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. Caution 0.5-second intervals cannot be generated with the 5.0-MHz main system clock. You should switch to the 32.768 kHz subsystem clock to generate 0.5-second intervals. (2) Interval timer Interrupt requests (INTTM3) are generated at the preset time interval. Table 10-1. Interval Timer Interval Time Interval Time 24 x 1/fW 25 x 1/fW 26 x 1/fW 27 x 1/fW 28 x 1/fW 29 x 1/fW Remark When operated at fXX = 5.0 MHz 410 s 819 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms When operated at fXX = 4.19 MHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms When operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms fXX : Main system clock frequency (fX or fX/2) fX : Main system clock oscillation frequency fXT : Subsystem clock oscillation frequency fW : Watch timer clock frequency (fXX/27 or fXT) User's Manual U10105EJ4V1UM00 195 CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Counter Control register 5 bits x 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) Configuration 10.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer. * Timer clock select register 2 (TCL2) * Watch timer mode control register (TMC2) (1) Timer clock select register 2 (TCL2) This register sets the watch timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and buzzer output frequency. 196 User's Manual U10105EJ4V1UM00 CHAPTER 10 WATCH TIMER Figure 10-1. Watch Timer Block Diagram TMC21 fW 214 * Selector fW Prescaler fW fW fW fW fW 7 24 25 26 2 28 fW 29 Selector Selector fXX /27 fXT Clear Selector 5-Bit Counter Clear INTWT fW 213 INTTM3 To 16-Bit Timer/ Event Counter 3 To LCD Controller/Driver TCL24 Timer Clock Select Register 2 TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Watch Timer Mode Control Register Internal Bus User's Manual U10105EJ4V1UM00 197 CHAPTER 10 WATCH TIMER Figure 10-2. Timer Clock Select Register 2 Format Symbol 7 6 5 4 3 0 2 1 0 Address FF42H After Reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS=1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 3 MCS=0 fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /212 (1.2 kHz) fX /23 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /211 (2.4 kHz) fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 Watch Timer Count Clock Selection TCL24 MCS=1 0 1 fXX/27 fXT (32.768 kHz) fX /27 (39.1 kHz) MCS=0 fX /28 (19.5 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 MCS=1 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Buzzer output disable fXX/29 fXX/210 fXX/211 Setting prohibited fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /212 (1.2 kHz) MCS=0 Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. fXX 2. fX 3. fXT 4. x : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency : Subsystem clock oscillation frequency : Don't care 5. MCS : Oscillation mode selection register bit 0 6. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. 198 User's Manual U10105EJ4V1UM00 CHAPTER 10 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H. Figure 10-3. Watch Timer Mode Control Register Format Symbol TMC2 7 0 6 5 4 3 2 1 0 Address FF4AH After Reset 00H R/W R/W TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 TMC20 Watch Operating Mode Selection 0 1 Normal operating mode (flag set at fW/214 ) Fast feed operating mode (flag set at fW/25) TMC21 Prescaler Operation Control 0 1 Clear after operation stop Operation enable TMC22 5-Bit Counter Operation Control 0 1 Clear after operation stop Operation enable Watch Flag Set Time Selection TMC23 fXX =5.0 MHz Operation 0 1 214/fW (0.4 sec) 213/fW (0.2 sec) fXX =4.19 MHz Operation 214/fW (0.5 sec) 213/fW (0.25 sec) fXT=32.768 kHz Operation 214/fW (0.5 sec) 213/fW (0.25 sec) Prescaler Interval Time Selection TMC26 TMC25 TMC24 fXX =5.0 MHz Operation 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 24/fW (410 s) 25/fW (819 s) 26/fW (1.64 ms) 27/fW (3.28 ms) 28/fW (6.55 ms) 29/fW (13.1 ms) Setting prohibited fXX =4.19 MHz Operation 24/fW (488 s) 25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms) fXT=32.768 kHz Operation 24/fW (488 s) 25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms) Other than above Caution When the watch timer is used, the prescaler should not be cleared frequently. Remark fW : Watch timer clock frequency (fXX/27 or fXT) fXX : Main system clock frequency (fX or fX/2) fX : Main system clock oscillation frequency fXT : Subsystem clock oscillation frequency User's Manual U10105EJ4V1UM00 199 CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/ HALT mode) can be cleared by setting WTIF to 1. When bit 2 (TIMC22) of the watch timer mode control register is set to 0, the 5-bit counter is cleared and the count operation stops. For simultaneous operation of the interval timer, zero-second start can be achieved by setting TMC22 to 0 (maximum error: 26.2 ms when operated at fXX = 5.0 MHz). 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupts repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (TMC24 to TMC26) of the watch timer mode control register. Table 10-3. Interval Timer Interval Time TMC26 TMC25 TMC24 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Interval Time 24 x 1/fW 25 x 1/fW 26 x 1/fW 27 x 1/fW 28 x 1/fW 29 x 1/fW Setting prohibited When operated at fXX = 5.0 MHz 410 s 819 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms When operated at fXX = 4.19 MHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms When operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms Other than above Remark fXX : Main system clock frequency (fX or fX/2) fX : Main system clock oscillation frequency fXT : Subsystem clock oscillation frequency fW : Watch timer clock frequency (fXX/27 or fXT) 200 User's Manual U10105EJ4V1UM00 CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM). (1) Watchdog timer mode An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable interrupt or RESET can be generated. Table 11-1. Watchdog Timer Inadvertent Program Overrun Detection Times Runaway Detection Time 211 x 1/fXX 212 x 1/fXX 213 x 1/fXX 214 x 1/fXX 215 x 1/fXX 216 x 1/fXX 217 x 1/fXX 219 x 1/fXX Remarks 1. fXX 2. fX MCS = 1 211 x 1/fX (410 s) 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency MCS = 0 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) 3. MCS : Oscillation mode selection register bit 0 4. Figures in parentheses apply to operation with fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 201 CHAPTER 11 WATCHDOG TIMER (2) Interval timer mode Interrupts are generated at the preset time intervals. Table 11-2. Interval Times Interval Time 211 x 1/fXX 212 x 1/fXX 213 x 1/fXX 214 x 1/fXX 215 x 1/fXX 216 x 1/fXX 217 x 1/fXX 219 x 1/fXX Remarks 1. fXX 2. fX MCS = 1 211 x 1/fX (410 s) 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency CS = 0 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) 3. MCS : Oscillation mode selection register bit 0 4. Figures in parentheses apply to operation with fX = 5.0 MHz. 202 User's Manual U10105EJ4V1UM00 CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Control register Configuration Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 11-1. Watchdog Timer Block Diagram Internal Bus fXX /23 Prescaler fXX fXX fXX fXX fXX fXX fXX 24 25 26 27 28 29 211 Selector TMMK4 RUN TMIF4 8-Bit Counter Control Circuit INTWDT Maskable Interrupt Request RESET INTWDT Non-Maskable Interrupt Request WDTM4 WDTM3 Watchdog Timer Mode Register 3 TCL22 TCL21 TCL20 Timer Clock Select Register 2 Internal Bus User's Manual U10105EJ4V1UM00 203 CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. * Timer clock select register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the watchdog timer count clock, TCL2 sets the watch timer count clock and buzzer output frequency. 204 User's Manual U10105EJ4V1UM00 CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format Symbol 7 6 5 4 3 0 2 1 0 Address FF42H After Reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS=1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 3 MCS=0 fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /212 (1.2 kHz) fX /23 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /211 (2.4 kHz) fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 Watch Timer Count Clock Selection TCL24 MCS=1 0 1 fXX/27 fXT (32.768 kHz) fX /27 (39.1 kHz) MCS=0 fX /28 (19.5 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 MCS=1 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Buzzer output disable fXX/2 9 MCS=0 fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /212 (1.2 kHz) fXX/210 fXX/211 Setting prohibited Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. fXX 2. fX 3. fXT 4. x : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency : Subsystem clock oscillation frequency : Don't care 5. MCS : Oscillation mode selection register bit 0 6. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. User's Manual U10105EJ4V1UM00 205 CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register Format Symbol 7 6 0 5 0 4 3 2 0 1 0 0 0 Address FFF9H After Reset 00H R/W R/W WDTM RUM WDTM4 WDTM3 WDTM4 WDTM3 0 0 0 1 Watchdog Timer Operation Mode Selection Note 1 Operation stop Interval timer mode (Maskable interrupt occurs upon generation of an overflow.) Watchdog timer mode 1 (Non-maskable interrupt occurs upon generation of an overflow.) Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow.) 1 0 1 1 RUN 0 1 Watchdog Timer Operation Mode Selection Note 2 Count stop Counter is cleared and counting starts. Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software. 2. Once set to 1, RUN cannot be cleared to 0 by software. Thus, once counting starts, it can only be stopped by RESET input. Caution When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is up to 0.5 % shorter than the time set by timer clock select register 2. 206 User's Manual U10105EJ4V1UM00 CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2). Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the set overrun time interval. The watchdog timer can be cleared and counting is started by setting RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable interrupt is generated according to the WDTM bit 3 (WDTM3) value. The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction. Cautions 1. The actual overrun detection time may be shorter than the set time by a maximum of 0.5 %. 2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is stopped. Table 11-4. Watchdog Timer Overrun Detection Time TCL22 0 0 0 0 1 1 1 1 TCL21 0 0 1 1 0 0 1 1 TCL20 0 1 0 1 0 1 0 1 Runaway Detection Time 211 x 1/fXX 212 x 1/fXX 213 x 1/fXX 214 x 1/fXX 215 x 1/fXX 216 x 1/fXX 217 x 1/fXX 219 x 1/fXX MCS = 1 211 x 1/fX (410 s) 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) MCS = 0 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) Remarks 1. fXX 2. fX : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency 3. MCS : Oscillation mode selection register bit 0 4. Figures in parentheses apply to operation with fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 207 CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 (WDTM3) and bit 4 (WDTM4) of the watchdog timer mode register (WDTM) are set to 1 and 0, respectively. When the watchdog timer operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag (TMPR4) are validated and the maskable interrupt (INTWDT) can be generated. Among maskable interrupts, the INTWDT default has the highest priority. The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless RESET input is applied. 2. The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0.5 %. 3. When the subsystem clock is selected for CPU clock, watchdog timer count operation is stopped. Table 11-5. Interval Timer Interval Time TCL22 0 0 0 0 1 1 1 1 TCL21 0 0 1 1 0 0 1 1 TCL20 0 1 0 1 0 1 0 1 Interval Time 211 x 1/fXX 212 x 1/fXX 213 x 1/fXX 214 x 1/fXX 215 x 1/fXX 216 x 1/fXX 217 x 1/fXX 219 x 1/fXX MCS = 1 211 x 1/fX (410 s) 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) MCS = 0 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) Remarks 1. fXX 2. fX : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency 3. MCS : Oscillation mode selection register bit 0 4. Figures in parentheses apply to operation with fX = 5.0 MHz. 208 User's Manual U10105EJ4V1UM00 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/P35 pin. Follow the procedure below to output clock pulses. (1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03) of TCL0. (2) Set the P35 output latch to 0. (3) Set bit 5 (PM35) of port mode register 3 to 0 (set to output mode). (4) Set bit 7 (CLOE) of timer clock select register 0 to 1. Caution Clock output cannot be used when setting P35 output latch to 1. Remark When clock output enable/disable is switched, the clock output control circuit does not output pulses with small widths (See the portions marked with * in Figure 12-1). Figure 12-1. Remote Controlled Output Application Example CLOE * PCL/P35 Pin Output * User's Manual U10105EJ4V1UM00 209 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Control register Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figure 12-2. Clock Output Control Circuit Block Diagram fXX fXX /2 fXX /22 fXX /24 fXX /25 fXX /26 fXX /27 fXT 4 Selector fXX /23 Synchronizing Circuit PCL /P35 CLOE TCL03 TCL02 TCL01 TCL00 Timer Clock Select Register 0 P35 Output Latch PM35 Port Mode Register 3 Internal Bus 210 User's Manual U10105EJ4V1UM00 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. * Timer clock select register 0 (TCL0) * Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TCL0 to 00H. Remark Cautions Besides setting PCL output clock, TCL0 sets the 16-bit timer register count clock. 1. Setting of the TI00/INTP0 pin valid edge is performed by external interrupt mode register 0, and selection of the sampling clock frequency is performed by the sampling clock selection register. 2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory manipulation instruction. 3. To read the count value when TI00 has been specified as the TM0 count clock, the value should be read from TM0, not from capture/compare register 01 (CR01). 4. When rewriting TCL0 to other data, stop the timer operation beforehand. User's Manual U10105EJ4V1UM00 211 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Figure 12-3. Timer Clock Select Register 0 Format Symbol TCL0 7 6 5 4 3 2 1 0 Address FF40H After Reset 00H R/W R/W CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 MCS=1 0 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fXT (32.768 kHz) fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fX (5.0 MHz) fX /2 (2.5 MHz) fX /22 (1.25 MHz) fX /23 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) MCS=0 fX /2 (2.5 MHz) fX /22 (1.25 MHz) fX /23 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) Other than above Setting prohibited 16-Bit Timer Register Count Clock Selection TCL06 TCL05 TCL04 MCS=1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TI00 (Valid edge specifiable) 2fXX fXX fXX/2 fXX/22 Setting prohibited fX (5.0 MHz) fX (5.0 MHz) MCS=0 fX /2 (2.5 MHz) fX /22 (1.25 MHz) fX /23 (625 kHz) fX /2 (2.5 MHz) fX /22 (1.25 MHz) Watch Timer Output (INTTM3) Setting prohibited Other than above CLOE 0 1 PCL Output Control Output disable Output enable Remarks 1. fXX 2. fX 3. fXT : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Oscillation mode selection register bit 0 7. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. 212 User's Manual U10105EJ4V1UM00 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register set port 3 input/output in 1-bit units. When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 12-4. Port Mode Register 3 Format After Reset FFH Symbol PM3 7 6 5 4 3 2 1 0 Address FF23H R/W R/W PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n P3n Pin Input/Output Mode Selection (n=0 to 7) 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) User's Manual U10105EJ4V1UM00 213 [MEMO] 214 User's Manual U10105EJ4V1UM00 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency. (1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2. (2) Set the P36 output latch to 0. (3) Set bit 6 (PM36) of port mode register 3 to 0 (Set to output mode). Caution Buzzer output cannot be used when setting P36 output latch to 1. 13.2 Buzzer Output Control Circuit Configuration The buzzer output control circuit consists of the following hardware. Table 13-1. Buzzer Output Control Circuit Configuration Item Control register Configuration Timer clock select register 2 (TCL2) Port mode register 3 (PM3) Figure 13-1. Buzzer Output Control Circuit Block Diagram fXX /29 fXX /210 fXX /211 Selector BUZ/P36 3 TCL27 TCL26 TCL25 Timer Clock Select Register 2 P36 Output Latch PM36 Port Mode Register 3 Internal Bus User's Manual U10105EJ4V1UM00 215 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. * Timer clock select register 2 (TCL2) * Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the buzzer output frequency, TCL2 sets the watch timer count clock and the watchdog timer count clock. 216 User's Manual U10105EJ4V1UM00 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format Symbol 7 6 5 4 3 0 2 1 0 Address FF42H After Reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS=1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 3 MCS=0 fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /212 (1.2 kHz) fX /2 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /211 (2.4 kHz) 3 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 Watch Timer Count Clock Selection TCL24 MCS=1 0 1 fXX/2 7 MCS=0 fX /28 (19.5 kHz) fX /2 (39.1 kHz) 7 fXT (32.768 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 MCS=1 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Buzzer output disable fXX/29 fXX/210 fXX/211 Setting prohibited fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /212 (1.2 kHz) MCS=0 Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. fXX 2. fX 3. fXT 4. x : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency : Subsystem clock oscillation frequency : don't care 5. MCS : Oscillation mode selection register bit 0 6. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. User's Manual U10105EJ4V1UM00 217 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 13-3. Port Mode Register 3 Format Symbol PM3 7 6 5 4 3 2 1 0 Address FF23H After Reset FFH R/W R/W PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n P3n Pin Input/Output Mode Selection (n=0 to 7) 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) 218 User's Manual U10105EJ4V1UM00 CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR). The following two ways are available to start A/D conversion. (1) Hardware start Conversion is started by trigger input (INTP3). (2) Software start Conversion is started by setting the A/D converter mode register. One channel of analog input is selected from ANI0 to ANI7 and A/D conversion is carried out. In the case of hardware start, A/D conversion operation stops when an A/D conversion operation ends. In the case of software start, the A/D conversion operation is repeated. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. 14.2 A/D Converter Configuration The A/D converter consists of the following hardware. Table 14-1. A/D Converter Configuration Item Analog input Configuration 8 Channels (ANI0 to ANI7) A/D converter mode register (ADM) Control register A/D converter input select register (ADIS) External interrupt mode register 1 (INTM1) Register Successive approximation register (SAR) A/D conversion result register (ADCR) User's Manual U10105EJ4V1UM00 219 CHAPTER 14 A/D CONVERTER * Figure 14-1. A/D Converter Block Diagram Internal Bus A/D Converter Input Select Register ADIS3 ADIS2 ADIS1 ADIS0 4 ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Series Resistor String Note 1 Note 2 Selector Selector Voltage Comparator Tap Selector Sample & Hold Circuit AVDD AVREF Successive Approximation Register (SAR) 3 ADM1-ADM3 AVSS INTP3/P03 ES40, ES41 Edge Detector Control Circuit INTAD INTP3 Trigger Enable CS 3 A / D Conversion Result Register (ADCR) TRG FR1 FR0 ADM3 ADM2 ADM1 A /D Converter Mode Register Internal Bus Notes 1. Selector to select the number of channels to be used for analog input. 2. Selector to select the channel for A/D conversion. 220 User's Manual U10105EJ4V1UM00 CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is set (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register. (2) A/D conversion result register (ADCR) This register holds the A/D conversion result. Each time A/D conversion terminates, the conversion result is loaded from the successive approximation register. ADCR is read with an 8-bit memory manipulation instruction. RESET input makes ADCR undefined. (3) Sample & hold circuit The sample & hold circuit samples each analog input sequentially applied from the input circuit and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage. (5) Series resistor string The series resistor string is in AVREF to AVSS and generates a voltage to be compared to the analog input. (6) ANI0 to ANI7 pins These are 8-channel analog input pins to input analog signals to undergo A/D conversion to the A/D converter. Pins other than those selected as analog input by the A/D converter input select register (ADIS) can be used as input/output ports. Caution Use ANI0 to ANI7 input voltages within the specified range. If a voltage higher than AVREF or lower than AVSS is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes indeterminate and may adversely affect the converted values of other channels. (7) AVREF pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF and AVSS. The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF pin to AVSS level in standby mode. (8) AVSS pin This is a GND potential pin of the A/D converter. Keep it at the same potential as the VSS pin when not using the A/D converter. (9) AVDD pin This is an A/D converter analog power supply pin. Keep it at the same potential as the VSS pin when not using the A/D converter. User's Manual U10105EJ4V1UM00 221 CHAPTER 14 A/D CONVERTER 14.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. * A/D converter mode register (ADM) * A/D converter input select register (ADIS) * External interrupt mode register 1 (INTM1) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger. ADM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADM to 01H. 222 User's Manual U10105EJ4V1UM00 CHAPTER 14 A/D CONVERTER Figure 14-2. A/D Converter Mode Register Format Symbol ADM 7 CS 6 TRG 5 FR1 4 3 2 1 0 Address FF80H After Reset 01H R/W R/W * FR0 ADM3 ADM2 ADM1 HSC ADM3 ADM2 ADM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D Conversion Time Selection FR1 FR0 HSC fX =5.0 MHz Operation MCS=1 0 0 1 1 0 1 0 0 1 1 0 1 80/fX (Setting prohibited Note 2 Note 1 fX =4.19 MHz Operation MCS=0 ) 160/fX (32.0 s) MCS=1 80/fX (19.1 s) MCS=0 160/fX (38.1 s) 40/fX (Setting prohibitedNote 2) 80/fX (Setting prohibited Note 2) 40/fX (Setting prohibited Note 2) 80/fX (19.1 s) 50/fX (Setting prohibitedNote 2) 100/fX (20.0 s) 100/fX (20.0 s) Setting prohibited 200/fX (40.0 s) 50/fX (Setting prohibited 100/fX (23.8 s) Note 2 ) 100/fX (23.8 s) 200/fX (47.7 s) Other than above TRG 0 1 External Trigger Selection No external trigger (software starts) Conversion started by external trigger (hardware starts) CS 0 1 A/D Conversion Operation Control Operation stop Operation start Notes 1. Set so that the A/D conversion time is 19.1 s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 s. Cautions 1. The following sequence is recommended for power consumption reduction of A/D converter when the standby function is used: Clear bit 7 (CS) to 0 first to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 2. When restarting the stopped A/D conversion operation, start the A/D conversion operation after clearing the interrupt request flag (ADIF) to 0. Remarks 1. fX : Main system clock oscillation frequency 2. MCS : Oscillation mode selection register bit 0 User's Manual U10105EJ4V1UM00 223 CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H. Cautions 1. Set the analog input channel in the following order. (1) Set the number of analog input channels with ADIS. (2) Using ADM, select one channel to undergo A/D conversion from among the channels set for analog input with ADIS. 2. No internal pull-up resistor can be connected to the channels set for analog input with ADIS, irrespective of the value of bit 1 (PUO1) of the pull-up resistor option register L. Figure 14-3. A/D Converter Input Select Register Format Symbol ADIS 7 0 6 0 5 0 4 0 3 2 1 0 Address FF84H After Reset 00H R/W R/W ADIS3 ADIS2 ADIS1 ADIS0 ADIS3 ADIS2 ADIS1 ADIS0 Number of Analog Input Channel Selection 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 No analog input channel (P10-P17) 1 channel (ANI0, P11-P17) 2 channel (ANI0, ANI1, P12-P17) 3 channel (ANI0-ANI2, P13-P17) 4 channel (ANI0-ANI3, P14-P17) 5 channel (ANI0-ANI4, P15-P17) 6 channel (ANI0-ANI5, P16, P17) 7 channel (ANI0-ANI6, P17) 8 channel (ANI0-ANI7) Setting prohibited Other than above 224 User's Manual U10105EJ4V1UM00 CHAPTER 14 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP5. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-4. External Interrupt Mode Register 1 Format Symbol INTM1 7 0 6 0 5 4 3 2 1 0 Address FFEDH After Reset 00H R/W R/W ES61 ES60 ES51 ES50 ES41 ES40 ES41 ES40 INTP3 Valid Edge Selection 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 ES50 INTP4 Valid Edge Selection 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges ES61 ES60 INTP5 Valid Edge Selection 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges User's Manual U10105EJ4V1UM00 225 CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM). (3) Sample the voltage input to the selected analog input channel with the sample & hold circuit. (4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until termination of A/D conversion. (5) Bit 7 of the successive approximation register (SAR) is set and the tap selector sets the series resistor string voltage tap to (1/2) AVREF. (6) The voltage difference between the series resistor string voltage tap and analog input is compared with a voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set. If the input is smaller than (1/2) AVREF, the MSB is reset. (7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. * Bit 7 = 1 : (3/4) AVREF * Bit 7 = 0 : (1/4) AVREF The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as follows. * Analog input voltage Voltage tap : Bit 6 = 1 * Analog input voltage Voltage tap : Bit 6 = 0 (8) Comparison of this sort continues up to bit 0 of SAR. (9) Upon completion of the comparison of 8 bits, any effective digital resultant value remains in SAR and the resultant value is transferred to and latched in the A/D conversion result register (ADCR). At the same time, the A/D conversion termination interrupt request (INTAD) can also be generated. 226 User's Manual U10105EJ4V1UM00 CHAPTER 14 A/D CONVERTER Figure 14-5. A/D Converter Basic Operation Conversion Time Sampling Time A/D Converter Operation Sampling A/D Conversion SAR Undefined 80H C0H or 40H Conversion Result ADCR Conversion Result INTAD A/D conversion operations are performed continuously until the CS bit is reset (0) by software. If a write to the ADM register is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (1), conversion starts again from the beginning. After RESET input, the value of ADCR is undefined. User's Manual U10105EJ4V1UM00 227 CHAPTER 14 A/D CONVERTER 14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in ADCR) is shown by the following expression. ADCR = INT ( or (ADCR - 0.5) x AVREF VIN < (ADCR + 0.5) x AVREF 256 256 VIN x 256 + 0.5) AVREF INT( ) : Function which returns integer parts of value in parentheses. VIN : Analog input voltage AVREF : AVREF pin voltage ADCR : ADCR register value Figure 14-6 shows the relation between the analog input voltage and the A/D conversion result. Figure 14-6. Relations between Analog Input Voltage and A/D Conversion Result 255 254 A/D Conversion Results (ADCR) 253 3 2 1 0 1 1 3 2 5 3 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 1 Input Voltage/AVREF 228 User's Manual U10105EJ4V1UM00 CHAPTER 14 A/D CONVERTER 14.4.3 A/D converter operating mode The operating mode is a select mode. One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and A/D conversion is executed. The following two ways are available to start A/D conversion. * Hardware start: Conversion is started by trigger input (INTP3). * Software start: Conversion is started by setting ADM. The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is simultaneously generated. (1) A/D conversion by hardware start When bit 6 (TRG) and bit 7 (CS) of ADM are set to 1, the A/D conversion standby state is set. When the external trigger signal (INTP3) is input, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, another operation is not started until a new external trigger signal is input. If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D conversion operation and waits for a new external trigger signal to be input. When the external trigger input signal is reinput, A/D conversion is carried out from the beginning. If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately. Figure 14-7. A/D Conversion by Hardware Start INTP3 ADM Rewrite CS=1, TRG=1 ADM Rewrite CS=1, TRG=1 A /D Conversion Standby State ANIn ANIn Standby State ANIn Standby State ANIm ANIm ANIm ADCR ANIn ANIn ANIn ANIm ANIm INTAD Remarks 1. n = 0, 1, ... , 7 2. m = 0, 1, ... , 7 User's Manual U10105EJ4V1UM00 229 CHAPTER 14 A/D CONVERTER (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, the next A/D conversion operation starts immediately. The A/D conversion operation continues repeatedly until new data is written to ADM. If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D conversion operation and starts A/D conversion on the newly written data. If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately. Figure 14-8. A/D Conversion by Software Start Conversion Start CS=1, TRG=0 ADM Rewrite CS=1, TRG=0 ADM Rewrite CS=0, TRG=0 A /D Conversion ANIn ANIn ANIn ANIm ANIm Conversion suspended Conversion results are not stored Stop ADCR ANIn ANIn ANIm INTAD Remarks 1. n = 0, 1, ... , 7 2. m = 0, 1, ... , 7 230 User's Manual U10105EJ4V1UM00 CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Cautions (1) Current consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AVREF pin at this time, this current must be cut in order to minimize the overall system power dissipation. In Figure 14-9, the power dissipation can be reduced by outputting a low-level signal to the output port in standby mode. However, there is no precision to the actual AVREF voltage, and therefore the conversion values themselves lack precision and can only be used for relative comparison. Figure 14-9. Example of Method of Reducing Current Consumption in Standby Mode VDD Output Port PD78064, 78064Y AVREF .. AVREF =VDD Series Resistor String AVSS (2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above AVREF or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel will be indeterminate. The conversion values of the other channels may also be affected. User's Manual U10105EJ4V1UM00 231 CHAPTER 14 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-10 in order to reduce noise. Figure 14-10. Analog Input Pin Disposition If there is possibility that noise whose level is AVREF or higher or AVSS or lower may enter, clamp with a diode with a small VF (0.3 V or less). Reference Voltage Input AVREF ANI0-ANI7 VDD C=100-1000 pF VDD AVDD AVSS VSS (4) Pins ANI0/P10 to ANI7/P17 The analog input pins ANI0 to ANI7 also function as input/output port (PORT1) pins. When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute a PORT1 input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (5) AVREF pin input impedance A series resistor string of approximately 10 k is connected between the AVREF pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVREF pin and the AVSS pin, and there will be a large reference voltage error. 232 User's Manual U10105EJ4V1UM00 CHAPTER 14 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADM rewrite, and when ADIF is read immediately after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended. When the A/D conversion is stopped and then resumed, clear the interrupt request flag (ADIF) before it is resumed. Figure 14-11. A/D Conversion End Interrupt Generation Timing ADM Rewrite (Start of ANIm Conversion) ADIF is set but ANIm conversion has not ended ADM Rewrite (Start of ANIn Conversion) A /D Conversion ANIn ANIn ANIm ANIm ADCR ANIn ANIn ANIm ANIm INTAD (7) AVDD pin The AVDD pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to ANI7/P17. Therefore, be sure to apply the same voltage as VDD to this pin even when the application circuit is designed so as to switch to a backup battery. Figure 14-12. Handling of AVDD Pin * AVREF VDD Main power supply AVDD Capacitor for back-up AVSS VSS User's Manual U10105EJ4V1UM00 233 [MEMO] 234 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) The PD78064 subseries incorporates two channels of serial interfaces. Differences between channels 0 and 2 are as follows (Refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2). Table 15-1. Differences between Channels 0 and 2 Serial Transfer Mode fXX/2, Clock selection Channel 0 fXX/22, fXX/23, External clock, baud rate generator output fXX/24, fXX/25, fXX/26, fXX/27, fXX/28, external clock, TO2 output Channel 2 3-wire serial I/O Transfer method MSB/LSB switchable as the start bit MSB/LSB switchable as the start bit Serial transfer end Transfer end flag interrupt request flag (CSIIF0) SBI (serial bus interface) Use possible 2-wire serial I/O UART (Asynchronous serial interface) None Serial transfer end interrupt request flag (SRIF) None Use possible User's Manual U10105EJ4V1UM00 235 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 15.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. * Operation stop mode * 3-wire serial I/O mode * SBI (serial bus interface) mode * 2-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out. Power consumption can be reduced. (2) 3-wire serial I/O mode (MSB-/LSB-first selectable) This mode is used for 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0) and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected regardless of their start bit recognition. This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X, 78K, and 17K series. (3) SBI (serial bus interface) mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). The SBI mode is in compliance with the NEC serial bus format. In the SBI mode, the transmitter outputs three kinds of data onto the serial data bus: "addresses" to selct a device to be communicated with, "commands" to give instructions to the selected device, and "data" to be actually sent or received. The receiver automatically distinguishes the received data into "address", "command", or "data", by hardware. This function enables the input/output ports to be used effectively and the application program serial interface control portions to be simplified. In this mode, the wake-up function for handshake and the output function of acknowledge and busy signals can also be used. 236 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in the increased number of available input/output ports. Figure 15-1. Serial Bus Interface (SBI) System Configuration Example VDD Master CPU Slave CPU1 SCK0 SB0 SCK0 SB0 Slave CPU2 SCK0 SB0 Slave CPUn SCK0 SB0 User's Manual U10105EJ4V1UM00 237 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 15.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 15-2. Serial Interface Channel 0 Configuration Item Register Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Timer clock select register 3 (TCL3) Serial operating mode register 0 (CSIM0) Control register Serial bus interface control register (SBIC) Interrupt timing specify register (SINT) Port mode register 2 (PM2) 238 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Figure 15-2. Serial Interface Channel 0 Block Diagram Internal Bus Serial Operating Mode Register 0 CSIE0 COI WUP CSIM CSIM CSIM CSIM CSIM 04 03 02 01 00 Serial Bus Interface Control Register Slave Address Register (SVA) SVAM Match BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Control Circuit SI0/SB0/ P25 PM25 Output Control Selector P25 Output Latch Selector PM26 Output Control Serial I/O Shift Register 0 (SIO0) CLR SET D Q SO0/SB1/ P26 Busy/ Acknowledge Output Circuit Bus Release/ Command/ Acknowledge Detector ACKD CMDD RELD WUP Interrupt Request Signal Generator P26 Output Latch SCK0/ P27 CLD PM27 Output Control Serial Clock Counter Serial Clock Control Circuit CSIM00 CSIM01 P27 Output Latch CLD SIC SVAM INTCSI0 TO2 Selector Selector fxx/2-fxx/28 CSIM00 CSIM01 4 TCL33 TCL32 TCL31 TCL30 Interrupt Timing Specify Register Timer Clock Select Register 3 Internal Bus Remark Output Control performs selection between CMOS output and N-ch open drain output. User's Manual U10105EJ4V1UM00 239 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation. In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. Note that, if a bus is driven in the SBI mode or 2-wire serial I/O mode, the bus pin must serve for both input and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address reception is carried out by setting bit 5 (WUP) of CSIM0 to 1). In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial bus interface control register (SBIC) is not cleared to 0. RESET input makes SIO0 undefined. (2) Slave address register (SVA) This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. SVA is set with an 8-bit memory manipulation instruction. The master device outputs a slave address for selection of a particular slave device to the connected slave device. These two data (the slave address output from the master device and the SVA value) are compared with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating mode register 0 (CSIM0) becomes 1. Address comparison can also be executed on the data of LSB-masked high-order 7 bits with bit 4 (SVAM) of the interrupt timing specify register (SINT). If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC) is cleared to 0. When bit 5 (WUP) of CSIM0 is 1, the interrupt request signal (INTCSI0) is generated only if the matching is detected. This interrupt request enables to recognize the generation of the communication request from the master device. Further, when SVA transmits data as master or slave device in the SBI or 2-wire serial I/O mode, errors are detected if any. RESET input makes SVA undefined. 240 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) Serial clock control circuit This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system clock is used, the circuit also controls clock output to the SCK0/P27 pin. (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates the interrupt request signal in the following cases. * In the 3-wire serial I/O mode and 2-wire serial I/O mode This circuit generates an interrupt request signal every eight serial clocks. * In the SBI mode When WUP is 0 ........... Generates an interrupt request signal every eight serial clocks. When WUP is 1 ........... Generates an interrupt request signal when the serial I/O shift register 0 (SIO0) value matches the slave address register (SVA) value after address reception. Remark WUP is wake-up function specify bit. It is bit 5 of serial operating mode register 0 (CSIM0). (7) Busy/acknowledge output circuit and bus release/command/acknowledge detector These two circuits output and detect various control signals in the SBI mode. These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode. User's Manual U10105EJ4V1UM00 241 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 15.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. * Timer clock select register 3 (TCL3) * Serial operating mode register 0 (CSIM0) * Serial bus interface control register (SBIC) * Interrupt timing specify register (SINT) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. 242 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Figure 15-3. Timer Clock Select Register 3 Format Symbol TCL3 7 1 6 0 5 0 4 0 3 2 1 0 Address FF43H After Reset 88H R/W R/W TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 MCS = 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) Other than above Setting prohibited Cautions 1. Set bit 4 to bit 6 to 0, and bit 7 to 1. 2. When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. fXX 2. fX : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency 3. MCS : Oscillation mode selection register bit 0 4. Figures in parentheses apply to operation with fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 243 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. * Figure 15-4. Serial Operating Mode Register 0 Format (1/2) Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/WNote 1 CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) 0 1 1 x 0 1 R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 Note 2 Note 2 Operation Mode 3-wire serial l/O mode Start Bit MSB LSB SIO/SB0/P25 Pin Function SI0Note 2 (Input) SO0/SB1/P26 Pin Function SO0 (CMOS output) SB1 (N-ch open-drain input/output) SCK0/P27 Pin Function SCK0 (CMOS input/output) 0 x 0 1 1 x 0 0 0 1 Note 3 Note 3 0 1 0 x x 0 0 0 1 SBI mode MSB P25 (CMOS input/output) SCK0 (CMOS input/output) SB0 (N-ch open-drain input/output) P26 (CMOS input/output) Note 3 Note 3 1 0 0 x x 0 1 Note 3 Note 3 0 1 1 x x 0 0 0 1 2-wire serial l/O mode MSB P25 (CMOS input/output) SB1 (N-ch open-drain input/output) Note 3 Note 3 1 0 0 x x 0 1 SB0 (N-ch open-drain input/output) SCK0 (N-ch open-drain input/output) P26 (CMOS input/output) Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as P25 (CMOS input/output) when used only for transmission. 3. Can be used freely as port function. Remark x : don't care 244 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Figure 15-4. Serial Operating Mode Register 0 Format (2/2) R/W WUP 0 1 Wake-up Function Control Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register data in SBI mode R COI 0 1 Slave Address Comparison Result FlagNote Slave address register not equal to serial I/O shift register 0 data Slave address register equal to serial I/O shift register 0 data R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enable Note When CSIE0 = 0, COI becomes 0. User's Manual U10105EJ4V1UM00 245 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 15-5. Serial Bus Interface Control Register Format (1/2) Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H After Reset 00H R/W R/WNote BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W RELT Used for bus release signal output. When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W CMDT Used for command signal output. When CMDT = 1, SO Iatch is cleared to (0). After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R RELD Bus Release Detection Set Conditions (RELD =1) Clear Conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied * When bus release signal (REL) is detected R CMDD Command Detection Set Conditions (CMDD = 1) Clear Conditions (CMDD = 0) * When transfer start instruction is executed * When bus release signal (REL) is detected * When CSIE0 = 0 * When RESET input is applied * When command signal (CMD) is detected R/W ACKT Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. Used as ACKE=0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0. Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits. Remark Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are 0 when read after data setting. 246 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Figure 15-5. Serial Bus Interface Control Register Format (2/2) R/W ACKE 0 Acknowledge Signal Output Control Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer 1 After completion of transfer Acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1). Acknowledge signal is output in synchronization with the falling edge of SCK0 just after execution of the instruction to be set to 1 (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output. R ACKD Acknowledge Detection Set Conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of SCK0 clock after completion of transfer Clear Conditions (ACKD = 0) * Falling edge of the SCK0 immediately after the busy mode is released while executing the transfer start instruction * When CSIE0 = 0 * When RESET input is applied R/W Note BSYE Synchronizing Busy Signal Output Control Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after execution of the instruction to be cleared to 0. Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal. 0 1 Note The busy mode can be canceled by start of serial interface transfer or reception of address signal. However, the BSYE flag is not cleared to 0. User's Manual U10105EJ4V1UM00 247 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 15-6. Interrupt Timing Specify Register Format Symbol SINT 7 0 6 CLD 5 SIC 4 SVAM 3 0 2 0 1 0 0 0 Address FF63H After Reset 00H R/W R/WNote 1 R/W SVAM 0 1 R/W SIC 0 1 INTCSI0 Interrupt Cause SelectionNote 2 CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 R CLD 0 1 SCK0 Pin LevelNote 3 Low level High level Notes 1. Bit 6 (CLD) is a read-only bit. 2. When using wake-up function in the SBI mode, set SIC to 0. 3. When CSIE0 = 0, CLD becomes 0. Caution Be sure to set bit 0 to bit 3 to 0. Remark SVA : Slave address register 248 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 15.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. * Operation stop mode * 3-wire serial I/O mode * SBI mode * 2-wire serial I/O mode 15.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. The serial I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register. In the operation stop mode, the P25/SI0/SB0, P26/SO0/SB1 and P27/SCK0 pins can be used as ordinary input/ output ports. (1) Register setting The operation stop mode is set with the serial operating mode register 0 (CSIM0). CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. The shaded area is used in the operation stop mode. Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/W CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled User's Manual U10105EJ4V1UM00 249 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 15.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0). (1) Register setting The 3-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0) and serial bus interface control register (SBIC). * (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. The shaded area is used in the 3-wire serial I/O mode. 250 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/WNote 1 CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) 0 1 1 x 0 1 R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 Note 2 Note 2 Operation Mode 3-wire serial l/O mode Start Bit MSB LSB SIO/SB0/P25 Pin Function SI0 (Input) Note 2 SO0/SB1/P26 Pin Function SO0 (CMOS output) SCK0/P27 Pin Function SCK0 (CMOS input/output) 0 x 0 1 1 x 0 0 0 1 1 1 0 1 SBI mode (See section 15.4.3, "SBI mode operation".) 2-wire serial I/O mode (See section 15.4.4, "2-wire serial I/O mode operation".) R/W WUP 0 1 Wake-up Function Control Note 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD=RELD=1) matches the slave address register data in SBI mode R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as P25 (CMOS input/output) when used only for transmission. 3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected. Remark x : don't care User's Manual U10105EJ4V1UM00 251 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the 3-wire serial I/O mode. Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H After Reset 00H R/W R/W BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W RELT When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W CMDT When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. 252 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the SI0 pin is latched in SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 15-7. 3-Wire Serial I/O Mode Timings SCK0 1 2 3 4 5 6 7 8 SI0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CSIIF0 End of Transfer Transfer Start at the Falling Edge of SCK0 The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status can be manipulated by setting the RELT and CMDT bits. However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 15.4.5 SCK0/P27 pin output manipulation). (3) Other signals Figure 15-8 shows RELT and CMDT operations. Figure 15-8. RELT and CMDT Operations SO0 latch RELT CMDT User's Manual U10105EJ4V1UM00 253 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 15-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register 0 (CSIM0). Figure 15-9. Circuit of Switching in Transfer Bit Order 7 6 Internal Bus 1 0 LSB-first MSB-first Read/Write Gate Read/Write Gate SO0 Latch SI0 Shift Register 0 (SIO0) D Q SO0 SCK0 Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (5) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1. * Internal serial clock is stopped or SCK0 is a high level after 8-bit serial transfer. Caution If CSIE0 is set to "1" after data write to SIO0, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. 254 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 15.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration function. This function enables devices to communicate using only two lines. Thus, when making up a serial bus with two or more microcontrollers and peripheral ICs, the number of ports to be used and the number of wires on the board can be decreased. The master device outputs three kinds of data to slave devices on the serial data bus: "addresses" to select a device to be communicated with, "commands" to instruct the selected device, and "data" which is actually required. The slave device can identify the received data into "address", "command", or "data", by hardware. This function enables the application program serial interface (channel 0) control portions to be simplified. The SBI function is incorporated into various devices including 75X-series devices and 78K-series 8-bit and 16bit single-chip microcontrollers. Figure 15-10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI and peripheral ICs are used. In SBI, the SB0 (SB1) serial data bus pin is an open-drain output pin and therefore the serial data bus line behaves in the same way as the wired-OR configuration. In addition, a pull-up resistor must be connected to the serial data bus line. When the SBI mode is used, refer to (10) SBI mode precautions (d) described later. Figure 15-10. Example of Serial Bus Configuration with SBI VDD Serial Clock SCK0 Master CPU Serial Data Bus SB0 (SB1) SB0 (SB1) Address 1 SCK0 Slave CPU SCK0 Slave CPU SB0 (SB1) Address 2 * * * * * * SCK0 Slave IC SB0 (SB1) Address N Caution When exchanging the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock line (SCK0) as well because serial clock line (SKC0) input/output switching is carried out asynchronously between the master and slave CPUs. User's Manual U10105EJ4V1UM00 255 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available. If these operations are to be controlled by software, the software must be heavily loaded. In SBI, a serial bus can be configured with two signal lines of serial clock SCK0 and serial data bus SB0 (SB1). Thus, use of SBI leads to reduction in the number of microcontroller ports and that of wirings and routings on the board. The SBI functions are described below. (a) Address/command/data identify function Serial data is distinguished into addresses, commands, and data. (b) Chip select function by address transmission The master executes slave chip selection by address transmission. (c) Wake-up function The slave can easily judge address reception (chip select judgment) with the wake-up function (which can be set/reset by software). When the wake-up function is set, the interrupt request signal (INTCSI0) is generated upon reception of a match address. Thus, when communication is executed with two or more devices, the CPU except the selected slave devices can operate regardless of underway serial communications. (d) Acknowledge signal (ACK) control function The acknowledge signal to check serial data reception is controlled. (e) Busy signal (BUSY) control function The busy signal to report the slave busy state is controlled. 256 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: "address", "command", and "data". Figure 15-11 shows the address, command, and data transfer timings. Figure 15-11. SBI Transfer Timings Address Transfer SCK0 8 9 SB0 (SB1) Bus Release Signal A7 A0 ACK BUSY Command Transfer Command Signal SCK0 9 SB0 (SB1) C7 C0 ACK BUSY READY Data Transfer SCK0 8 9 SB0 (SB1) D7 D0 ACK BUSY READY The bus release signal and the command signal are output by the master device. BUSY is output by the slave signal. ACK can be output by either the master or slave device (normally, the 8-bit data receiver outputs). Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset. User's Manual U10105EJ4V1UM00 257 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device. Figure 15-12. Bus Release Signal SCK0 SB0 (SB1) H The bus release signal indicates that the master device is going to transmit an address to the slave device. The slave device incorporates hardware to detect the bus release signal. (b) Command signal (CMD) The command signal is a signal with the SB0 (SB1) line which has changed from the high level to the low level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device. Figure 15-13. Command Signal SCK0 SB0 (SB1) H The slave device incorporates hardware to detect the command signal. 258 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 15-14. Addresses SCK0 SB0 (SB1) 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 A0 Address Bus Release Signal Command Signal 8-bit data following bus release and command signals is defined as an "address". In the slave device, this condition is detected by hardware and whether or not 8-bit data matches the own specification number (slave address) is checked by hardware. If the 8-bit data matches the slave address, the slave device has been selected. After that, communication with the master device continues until a release instruction is received from the master device. Figure 15-15. Slave Selection with Address Master Slave 2 address transmission Slave 1 Not selected Slave 2 Selected Slave 3 Not selected Slave 4 Not selected User's Manual U10105EJ4V1UM00 259 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 15-16. Commands SCK0 SB0 (SB1) 1 C7 2 C6 3 C5 4 C4 5 C3 6 C2 7 C1 8 C0 Command Signal Command Figure 15-17. Data SCK0 SB0 (SB1) 1 D7 2 D6 3 D5 4 D4 Data 5 D3 6 D2 7 D1 8 D0 8-bit data following a command signal is defined as "command" data. 8-bit data without command signal is defined as "data". Command and data operation procedures are allowed to determine by user according to communications specifications. 260 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 15-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] SCK0 8 9 10 11 * SB0 (SB1) ACK [When output in synchronization with 9th clock SCK0] SCK0 8 9 SB0 (SB1) ACK The acknowledge signal is one-shot pulse to be generated at the falling edge of SCK0 after 8-bit data transfer. It can be positioned anywhere and can be synchronized with any clock SCK0. After 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge signal. If the acknowledge signal is not returned for the preset period of time after data transmission, it can be judged that data reception has not been carried out correctly. User's Manual U10105EJ4V1UM00 261 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception. The READY signal is intended to report to the master device that the slave device is ready for data transmission/reception. Figure 15-19. BUSY and READY Signals SCK0 8 9 SB0 (SB1) ACK BUSY READY In SBI, the slave device notifies the master device of the busy state by setting SB0 (SB1) line to the low level. The BUSY signal output follows the acknowledge signal output from the master or slave device. It is set/reset at the falling edge of SCK0. When the BUSY signal is reset, the master device automatically terminates the output of SCK0 serial clock. When the BUSY signal is reset and the READY signal is set, the master device can start the next transfer. 262 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. The shaded area is used in the SBI mode. Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/WNote 1 * CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) 0 1 1 x 0 1 R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 Operation Mode Start Bit SI0/SB0/P25 Pin Function SO0/SB1/P26 Pin Function SCK0/P27 Pin Function 0 x 3-wire serial I/O mode (15.4.2, "3-wire serial I/O mode operation.") Note 2 Note 2 0 1 0 x x 0 0 0 1 SBI mode MSB P25 (CMOS input/output) SB1 (N-ch open-drain input/output) Note 2 Note 2 1 0 0 x x 0 1 SB0 (N-ch open-drain input/output) SCK0 (CMOS input/output) P26 (CMOS input/output) 1 1 2-wire serial I/O mode (see section 15.4.4, "2-wire serial I/O mode operation.") R/W WUP 0 1 Wake-up Function Control Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD=RELD=1) matches the slave address register data in SBI mode R COI 0 1 Slave Address Comparison Result FlagNote3 Slave address register not equal to serial I/O shift register 0 data Slave address register equal to serial I/O shift register 0 data R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as a port. 3. When CSIE0=0, COI becomes 0. Remark x : don't care User's Manual U10105EJ4V1UM00 263 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the SBI mode. Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H After Reset 00H R/W R/WNote BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W RELT Used for bus release signal output. When RELT = 1, SO Iatch is set to (1). After SO latch setting, automatically cleared to (0). Also cleared to 0 when CSIE0 = 0. R/W CMDT Used for command signal output. When CMDT = 1, SO Iatch is cleared to (0). After SO latch clearance, automatically cleared to (0). Also cleared to 0 when CSIE0 = 0. R RELD Bus Release Detection Set Conditions (RELD = 1) Clear Conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied * When bus release signal (REL) is detected R CMDD Command Detection Set Conditions (CMDD = 1) Clear Conditions (CMDD = 0) * When transfer start instruction is executed * When bus release signal (REL) is detected * When CSIE0 = 0 * When RESET input is applied * When command signal (CMD) is detected R/W ACKT Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution of the instruction to be set to (1) and, after acknowledge signal output, automatically cleared to (0). Used as ACKE=0. Also cleared to (0) upon start of serial interface transfer or when CSIE0 = 0. R/W ACKE 0 Acknowledge Signal Output Control Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer Acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1). Acknowledge signal is output in synchronization with falling edge clock of SCK0 just after execution of the instruction to be set to 1 (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output. 1 After completion of transfer Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits. Remark Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting. (Continued) 264 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) R ACKD Acknowledge Detection Set Conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of SCK0 clock after completion of transfer Clear Conditions (ACKD = 0) * SCK0 fall immediately after the busy mode is released during the transfer start instruction execution. * When CSIE0 = 0 * When RESET input is applied * R/W Note BSYE Synchronizing Busy Signal Output Control Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after execution of the instruction to be cleared to (0). Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal. 0 1 Note Busy mode can be cleared by start of serial interface transfer or reception of address signal. However, BSYE flag is not cleared to 0. User's Manual U10105EJ4V1UM00 265 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. The shaded area is used in the SBI mode. Symbol SINT 7 0 6 CLD 5 SIC 4 SVAM 3 0 2 0 1 0 0 0 Address FF63H After Reset 00H R/W R/WNote 1 R/W SVAM 0 1 R/W SIC 0 1 INTCSI0 Interrupt Factor SelectionNote 2 CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 R CLD 0 1 SCK0 Pin LevelNote 3 Low level High level Notes 1. Bit 6 (CLD) is a read-only bit. 2. When using wake-up function in the SBI mode, set SIC to 0. 3. When CSIE0 = 0, CLD becomes 0. Caution Be sure to set bit 0 to bit 3 to 0. Remark SVA : Slave address register 266 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (4) Various signals Figures 15-20 to 15-25 show various signals and flag operations in SBI. Table 15-3 lists various signals in SBI. Figure 15-20. RELT, CMDT, RELD, and CMDD Operations (Master) Slave address write to SIO0 (Transfer Start Instruction) SIO0 SCK0 SB0 (SB1) RELT CMDT RELD CMDD Figure 15-21. RELD and CMDD Operations (Slave) Write FFH to SIO0 (Transfer start instruction) SIO0 A7 A6 A1 A0 * Transfer start instruction SCK0 1 2 7 8 9 READY SB0 (SB1) A7 A6 A1 A0 ACK When addresses match Slave address RELD When addresses do not match CMDD User's Manual U10105EJ4V1UM00 267 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Figure 15-22. ACKT Operation SCK0 SB0 (SB1) ACKT 6 D2 7 D1 8 D0 9 ACK ACK signal is output for a period of one clock just after setting When set during this period Caution Do not set ACKT before termination of transfer. 268 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Figure 15-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer SCK0 1 2 7 8 9 SB0 (SB1) ACKE D7 D6 D2 D1 D0 ACK ACK signal is output at 9th clock When ACKE = 1 at this point (b) When set after completion of transfer SCK0 6 7 8 9 SB0 (SB1) D2 D1 D0 ACK ACK signal is output for a period of one clock just after setting ACKE If set during this period and ACKE = 1 at the falling edge of the next SCK0 (c) When ACKE = 0 upon completion of transfer SCK0 SB0 (SB1) 1 D7 2 D6 D2 7 D1 8 D0 9 ACK signal is not output ACKE When ACKE = 0 at this point (d) When "ACKE = 1" period is short SCK0 SB0 (SB1) D2 D1 D0 ACK signal is not output ACKE If set and cleared during this period and ACKE = 0 at the falling edge of SCK0 User's Manual U10105EJ4V1UM00 269 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Figure 15-24. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 Transfer Start Instruction SIO0 Transfer Start SCK0 6 7 8 9 SB0 (SB1) D2 D1 D0 ACK ACKD (b) When ACK signal is output after 9th clock of SCK0 Transfer Start Instruction SIO0 Transfer Start SCK0 6 7 8 9 SB0 (SB1) D2 D1 D0 ACK ACKD (c) Clear timing when transfer start is instructed in BUSY Transfer Start Instruction SIO0 SCK0 6 7 8 9 SB0 (SB1) D2 D1 D0 ACK BUSY D7 D6 ACKD Figure 15-25. BSYE Operation SCK0 6 7 8 9 SB0 (SB1) D2 D1 D0 ACK BUSY BSYE When BSYE = 1 at this point If reset during this period and BSYE = 0 at the falling edge of SCK0 270 User's Manual U10105EJ4V1UM00 Table 15-3. Various Signals in SBI Mode (1/2) Signal Name Output Device Definition Timing Chart Output Condition Effects on Flag Meaning of Signal CMD signal is output to indicate that transmit data is an address. i) Transmit data is an address after REL signal output. ii) REL signal is not output and transmit data is an command. Bus release signal (REL) Master SB0 (SB1) rising edge when SCK0 = 1 SCK0 SB0 (SB1) "H" * RELT set * RELD set * CMDD clear CHAPTER 15 Command signal (CMD) User's Manual U10105EJ4V1UM00 Master SB0 (SB1) falling edge when SCK0 = 1 SCK0 SB0 (SB1) "H" * CMDT set * CMDD set SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Acknowledge signal (ACK) Master/ slave Low-level signal to be output to SB0 (SB1) during one-clock period of SCK0 after completion of serial reception [Synchronous BUSY signal] Low-level signal to be output to SB0 (SB1) following Acknowledge signal 1 ACKE = 1 2 ACKT set [Synchronous BUSY output] * ACKD set Completion of reception Busy signal (BUSY) Slave SCK0 9 ACK BUSY * BSYE = 1 -- Serial receive disable because of processing SB0 (SB1) D0 ACK BUSY READY Ready signal (READY) Slave High-level signal to be output to SB0 (SB1) before serial transfer start and after completion of serial transfer SB0 (SB1) D0 READY 1 BSYE = 0 2 Execution of instruction for data write to SIO0 (transfer start instruction) 3 Address signal reception -- Serial receive enable 271 272 Signal Name Output Device Definition Serial clock (SCK0) Master Address (A7 to A0) Master 8-bit data to be transferred in synchronization with SCK0 after output of REL and CMD signals User's Manual U10105EJ4V1UM00 Table 15-3. Various Signals in SBI Mode (2/2) Timing Chart Output Condition Effects on Flag Meaning of Signal Synchronous clock to output address/command/ data, ACK signal, synchroSCK0 nous BUSY signal, etc. Address/command/data are SB0 (SB1) transferred with the first eight synchronous clocks. 1 2 7 8 9 10 Timing of signal output to serial data bus CHAPTER 15 SCK0 1 2 7 8 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) SB0 (SB1) REL CMD Commands (C7 to C0) Master 8-bit data to be transferred in synchronization with SCK0 after output of only CMD signal without REL signal output SCK0 1 2 7 8 SB0 (SB1) CMD Address value of When CSIE0 = 1, slave device on the execution of instruction for CSIIF0 set (rising serial bus data write to edge of 9th clock SIO0 (serial of SCK0)Note 1 transfer start instruction)Note 2 Instructions and messages to the slave device Data (D7 to D0) Master/ slave 8-bit data to be transferred in synchronization with SCK0 without output of REL and CMD signals SCK0 1 2 7 8 SB0 (SB1) Numeric values to be processed with slave or master device Notes 1. When WUP = 0, CSIIF0 is set at the rising edge of the 9th clock of SCK0. When WUP = 1, an address is received. Only when the address matches the slave address register (SVA) value, CSIIF0 is set. 2. In BUSY state, transfer starts after the READY state is set. CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (5) Pin configuration The serial clock pin (SCK0) and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............. Serial clock input/output pin 1 2 Master ... CMOS and push-pull output Slave ...... Schmitt input Both master and slave devices have an N-ch open drain output and a Schmitt input. Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary. Figure 15-26. Pin Configuration Slave Device (b) SB0 (SB1) ..... Serial data input/output dual-function pin Master Device (Clock Output) Clock Input Serial Clock (Clock Input) SCK0 Clock Output SCK0 N-ch Open Drain SO0 SB0 (SB1) RL Serial Data Bus SB0 (SB1) N-ch Open Drain SO0 SI0 SI0 Caution Because the N-ch open-drain must be turned off at time of data reception, write FFH to SIO0 in advance. The N-ch open-drain can be turned off at any time of transfer. However, when the wake-up function specify bit (WUP) = 1, the N-ch transistor is always turned off. Thus, it is not necessary to write FFH to SIO0. User's Manual U10105EJ4V1UM00 273 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (6) Address match detection method In the SBI mode, a particular slave device is selected by address communication from the master device and communication is started. Address match detection is executed by hardware. With the slave address register (SVA), CSIIF0 is set in the wake-up state (WUP = 1) only when the address transmitted from the master device matches the value set to SVA. Cautions 1. Slave selection/non-selection is detected by matching of the slave address received after bus release (RELD = 1). For this match detection, match interrupt (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. 2. When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (7) Error detection In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, the serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following way. (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred. (b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged to have occurred. (8) Communication operation In the SBI mode, the master device selects normally one slave device as communication target from among two or more devices by outputting an "address" to the serial bus. After the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave devices. Figures 15-27 to 15-30 show data communication timing charts. Shift operation of the shift register is carried out at the falling edge of serial clock (SCK0). Transmit data is latched into the SO0 latch and is output with MSB set as the first bit from the SB0/P25 or SB1/P26 pin. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into the shift register. 274 User's Manual U10105EJ4V1UM00 Figure 15-27. Address Transmission from Master Device to Slave Device (WUP = 1) Master Device Processing (Transmitter) Program Processing CMDT Set RELT Set CMDT Set Write to SIO0 Interrupt Servicing (Preparation for the Next Serial Transfer) CHAPTER 15 Hardware Operation Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) Transfer Line SCK0 Pin 1 2 3 4 5 6 7 8 9 User's Manual U10105EJ4V1UM00 SB0 (SB1) Pin A7 A6 A5 A4 A3 A2 A1 A0 ACK BUSY READY Address Slave Device Processing (Receiver) Program Processing WUP0 ACKT Set BUSY Clear Hardware Operation CMDD CMDD CMDD Set Clear Set RELD Set Serial Reception INTCSI0 Generation ACK BUSY Output Output BUSY Clear (When SVA = SIO0) 275 276 Master Device Processing (Transmitter) Program Processing Hardware Operation Transfer Line SCK0 Pin User's Manual U10105EJ4V1UM00 Figure 15-28. Command Transmission from Master Device to Slave Device CMDT Set Write to SIO0 Interrupt Servicing (Preparation for the Next Serial Transfer) CHAPTER 15 Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 1 2 3 4 5 6 7 8 9 SB0 (SB1) Pin C7 C6 C5 C4 C3 C2 C1 C0 ACK BUSY READY Command Slave Device Processing (Receiver) Program Processing SIO0 Read Command ACKT analysis Set BUSY Clear Hardware Operation CMDD Set Serial Reception INTCSI0 Generation ACK Output BUSY Output BUSY Clear Figure 15-29. Data Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Program Processing Write to SIO0 Interrupt Servicing (Preparation for the Next Serial Transfer) CHAPTER 15 Hardware Operation Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Transfer Line SCK0 Pin 1 2 3 4 5 6 7 8 9 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) User's Manual U10105EJ4V1UM00 SB0 (SB1) Pin D7 D6 D5 D4 D3 Data D2 D1 D0 ACK BUSY READY Slave Device Processing (Receiver) Program Processing SIO0 Read ACKT Set BUSY Clear Hardware Operation Serial Reception INTCSI0 Generation ACK Output BUSY Output BUSY Clear 277 278 Master Device Processing (Receiver) Program Processing Hardware Operation Transfer Line SCK0 Pin User's Manual U10105EJ4V1UM00 Figure 15-30. Data Transmission from Slave Device to Master Device FFH Write to SIO0 SIO0 Read ACKT FFH Write Set to SIO0 Receive data processing CHAPTER 15 SCK0 Stop Serial Reception INTCSI0 Generation ACK Output Serial Reception SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 1 2 3 4 5 6 7 8 9 1 2 SB0 (SB1) Pin BUSY READY D7 D6 D5 D4 D3 Data D2 D1 D0 ACK BUSY READY D7 D6 Slave Device processing (Transmitter) Program Processing Write to SIO0 Write to SIO0 Hardware Operation BUSY Clear Serial Transmission INTCSI0 Generation ACKD Set BUSY Output BUSY Clear CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch transistor must be turned off for data reception, write FFH to SIO0 in advance. However, when the make-up function specify bit (WUP) = 1, the N-ch transistor is always turned off. Thus, it is not necessary to write FFH to SIO0. 3. If data is written to SIO0 when the slave is busy, the data is not lost. When the busy state is cleared and SB0 (or SB1) input is set to the high level (READY) state, transfer starts. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. User's Manual U10105EJ4V1UM00 279 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (10) SBI mode precautions (a) Slave selection/non-selection is detected by match detection of the slave address received after bus release (RELD = 1). For this match detection, match interrupt (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. (b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (c) If WUP is set to 1 during BUSY signal output, BUSY is not cleared. In SBI, the BUSY signal continues to be output after BUSY clear instruction generation to the falling edge of the next serial clock (SCK0). Before setting WUP to 1, be sure to clear BUSY and then check that the SB0 (SB1) has become highlevel. (d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set the P25 and P26 output latches to 1. <2> Set bit 0 (RELT) of the serial bus interface control register to 1. <3> Reset the P25 and P26 output latches from 1 to 0. (e) When device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> Detect acknowledge signal (ACK) or interrupt request signal generation. <2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode. <3> Read out the pin state (when the pin level is high, the READY state is set). After the detection of the READY state, set the port mode register to 0 and return to the output mode. 280 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 15.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 15-31. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode VDD VDD Master Slave SCK0 SCK0 SB0 (SB1) SB0 (SB1) User's Manual U10105EJ4V1UM00 281 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). * (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. The shaded area is used in the 2-wire serial I/O mode. Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/WNote 1 CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) 0 1 1 x 0 1 R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 Operation Mode Start Bit SIO/SB0/P25 Pin Function SO0/SB1/P26 Pin Function SCK0/P27 Pin Function 0 1 x 0 3-wire Serial I/O mode (See Section 15.4.2, "3-wire serial I/O mode operation" SBI mode (See section 15.4.3, "SBI mode operation" Note 2 Note 2 0 1 1 1 x x 0 0 0 1 2-wire serial l/O mode MSB P25 (CMOS input/output SB0 (N-ch open-drain input/output) SB1 (N-ch open-drain input/output) P26 (CMOS input/output) Note 2 Note 2 0 0 x x SCK0 (N-ch open-drain input/output) 0 1 R/W WUP 0 1 Wake-up Function Control Note 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD=RELD=1) matches the slave address register data in SBI mode R COI 0 1 Slave Address Comparison Result FlagNote4 Slave address register not equal to serial I/O shift register 0 data Slave address register equal to serial I/O shift register 0 data R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used freely as port function. 3. Be sure to set WUP to 0 when the 2-wire serial I/O mode. 4. When CSIE0=0, COI becomes 0. Remark x : don't care 282 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the 2-wire serial I/O mode. Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H After Reset 00H R/W R/W BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W RELT When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W CMDT When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. User's Manual U10105EJ4V1UM00 283 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) * (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. The shaded area is used in the 2-wire serial I/O mode. Symbol SINT 7 0 6 CLD 5 SIC 4 SVAM 3 0 2 0 1 0 0 0 Address FF63H After Reset 00H R/W R/WNote 1 R/W SIC 0 1 INTCSI0 Interrupt Factor Selection CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer R CLD 0 1 SCK0 Pin LevelNote 2 Low level High level Notes 1. Bit 6 (CLD) is a read-only bit. 2. When CSIE0 = 0, CLD becomes 0. Caution Be sure to set bit 0 to bit 3 to 0. 284 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/ P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into the shift register at the rising edge of SCK0. Upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 15-32. 2-Wire Serial I/O Mode Timings SCK0 1 2 3 4 5 6 7 8 SB0 (SB1) D7 D6 D5 D4 D3 D2 D1 D0 CSIIF0 End of Transfer Transfer Start at the Falling Edge of SCK0 The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain input/output and thus it must be externally connected to a pull-up resistor. Because it is necessary to turn off the N-ch transistor for data reception, write FFH to SIO0 in advance. The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be manipulated by setting the RELT and CMDT bits. However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 15.4.5 SCK0/P27 pin output manipulation). User's Manual U10105EJ4V1UM00 285 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) (3) Other signals Figure 15-33 shows RELT and CMDT operations. Figure 15-33. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch transistor must be turned off for data reception, write FFH to SIO0 in advance. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. (5) Error detection In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, SIO0. Thus, transmit error can be detected in the following way. (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred. (b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged to have occurred. 286 User's Manual U10105EJ4V1UM00 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78064 Subseries) 15.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any number of SCK0 to be set by software. (SI0/SB0 and SO0/SB1 pin to be controlled with the RELT and CMDT bits of SBIC.) SCK0/P27 pin output manipulating procedure is described below. 1 2 Set the serial operating mode register 0 (CSIM0) (SCK0 pin is set in the output mode and serial operation is enabled). While serial transfer is suspended, SCK0 is set to 1. Manipulate the content of the P27 output latch by executing the bit manipulation instruction. Figure 15-34. SCK0/P27 Pin Configuration Set by bit manipulation instruction SCK0/P27 To Internal Circuit P27 Output Latch * When CSIE0 = 1 and CSIM01 and CSIM00 are 1 and 0, or 1 and 1. SCK0 (1 when transfer stops) From Serial Clock Control Circuit User's Manual U10105EJ4V1UM00 287 [MEMO] 288 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) * The PD78064Y subseries incorporates two channels of serial interfaces. Differences between channels 0 and 2 are as follows (Refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2). Table 16-1. Differences between Channels 0 and 2 Serial Transfer Mode fXX/2, Clock selection Channel 0 fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXX/28, external clock, TO2 output Channel 2 External clock, baud rate generator output 3-wire serial I/O Transfer method MSB/LSB switchable as the start bit MSB/LSB switchable as the start bit Serial transfer end Transfer end flag interrupt request flag (CSIIF0) I2C bus (Inter IC Bus) Use possible 2-wire serial I/O UART (Asynchronous serial interface) None Serial transfer end interrupt request flag (SRIF) None Use possible User's Manual U10105EJ4V1UM00 289 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * I2C (Inter IC) bus mode (1) Operation stop mode This mode is used when serial transfer is not carried out. Power consumption can be reduced. (2) 3-wire serial I/O mode (MSB-/LSB-first selectable) This mode is used for 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0) and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected regardless of their start bit recognition. This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X, 78K, and 17K series. (3) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in the increased number of available input/output ports. 290 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (4) I2C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I2C bus format. In this mode, the transmitter outputs three kinds of data onto the serial data bus: "start condition", "data", and "stop condition", to be actually sent or received. The receiver automatically distinguishes the received data into "start condition", "data", or "stop condition", by hardware. Figure 16-1. Serial Bus Configuration Example Using I2C Bus VDD Master CPU VDD Slave CPU1 SCL SDA0 (SDA1) SCL SDA0 (SDA1) Slave CPU2 SCL SDA0 (SDA1) Slave CPUn SCL SDA0 (SDA1) User's Manual U10105EJ4V1UM00 291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-2. Serial Interface Channel 0 Configuration Item Register Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Timer clock select register 3 (TCL3) Serial operating mode register 0 (CSIM0) Control register Serial bus interface control register (SBIC) Interrupt timing specify register (SINT) Port mode register 2 (PM2) 292 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-2. Serial Interface Channel 0 Block Diagram Internal Bus Serial Bus Interface Control Register Slave Address Register (SVA) SVAM Match BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Serial Operating Mode Register 0 CSIE0 COI WUP CSIM CSIM CSIM CSIM CSIM 04 03 02 01 00 BSYE Control Circuit SI0/SB0/ SDA0/P25 PM25 Output Control Selector P25 Output Latch Selector Serial I/O Shift Register 0 (SIO0) CLR SET D Q SO0/SB1/ SDA1/P26 PM26 Output Control Acknowledge Output Circuit Stop Condition/ Start Condition/ Acknowledge Detector ACKD CMDD RELD WUP Interrupt Request Signal Generator TO2 SCK0/ SCL/P27 CLD PM27 P26 Output Latch Serial Clock Counter Serial Clock Control Circuit CSIM00 CSIM01 1/16 Divider 2 INTCSI0 Output Control Selector Selector fxx/2-fxx/28 CSIM00 CSIM01 4 P27 Output Latch CLD SIC SVAM CLC WREL WAT1 WAT0 TCL33 TCL32 TCL31 TCL30 Interrupt Timing Specify Register Timer Clock Select Register 3 Internal Bus Remark Output Control performs selection between CMOS output and N-ch open drain output. User's Manual U10105EJ4V1UM00 293 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation. In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. Note that, if a bus is driven in the I2C bus mode or 2-wire serial I/O mode, the bus pin must serve for both input and output. Therefore, the transmission N-ch transistor of the device which will start reception of data must be turned off beforehand. Consequently, write FFH to SIO0 in advance. In the I2C bus mode, set SIO0 to FFH with bit 7 (BSYE) of the serial bus interface control register (SBIC) set to 0. RESET input makes SIO0 undefined. (2) Slave address register (SVA) This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. SVA is set with an 8-bit memory manipulation instruction. The master device outputs a slave address for selection of a particular slave device to the connected slave device. These two data (the slave address output from the master device and the SVA value) are compared with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating mode register 0 (CSIM0) becomes 1. Address comparison can also be executed on the data of LSB-masked high-order 7 bits with bit 4 (SVAM) of the interrupt timing specify register (SINT). If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC) is cleared to 0. When bit 5 (WUP) of CSIM0 is 1, the interrupt request signal (INTCSI0) is generated only if the matching is detected. This interrupt request enables to recognize the generation of the communication request from the master device. Further, when SVA transmits data as master or slave device in the the I2C bus mode or 2-wire serial I/O mode, errors are detected if any. RESET input makes SVA undefined. (3) SO0 latch This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by software. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) Serial clock control circuit This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system clock is used, the circuit also controls clock output to the SCK0/SCL/P27 pin. 294 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates interrupt request signals according to the settings of interrupt timing specification register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operation mode register 0 (CSIM0) bit 5 (WUP), as shown in Table 16-3. (7) Acknowledge output circuit and stop condition/start condition/acknowledge detector These two circuits output and detect various control signals in the I2C mode. These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode. Table 16-3. Serial Interface Channel 0 Interrupt Request Signal Generation Serial Transfer mode 3-wire or 2-wire serial I/O mode BSYE WUP WAT1 WAT0 ACKE 0 0 0 0 0 Description An interrupt request signal is generated each time 8 serial clocks are counted. Other than above I2C bus mode (transmit) 0 0 1 0 0 Setting prohibited An interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). Normally, during transmission the settings WAT21, WAT0=1, 0, are not used. They are used only when wanting to coordinate receive time and processing systematically using software. ACK information is generated by the receiving side, thus ACKE should be set to 0 (disable). 1 1 0 An interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). ACK information is generated by the receiving side, thus ACKE should be set to 0 (disable). Other than above I2C bus mode (receive) 1 0 1 0 0 Setting prohibited An interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). ACK information is output by manipulating ACKT by software after an interrupt is generated. 1 1 0/1 An interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). To automatically generate ACK information, preset ACKE to 1 before transfer start. However, in the case of the master, set ACKE to 0 (disable) before receiving the last data. 1 1 1 1 1 After address is received, if the values of the serial I/O shift register 0 (SI00) and the slave address register (SVA) match, an interrupt request signal is generated. To automatically generate ACK information, preset ACKE to 1 (enable) before transfer start. Other than above Remark Setting prohibited BSYE: Bit 7 of serial bus interface control register (SBIC) ACKE: Bit 5 of serial bus interface control register (SBIC) User's Manual U10105EJ4V1UM00 295 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. * Timer clock select register 3 (TCL3) * Serial operating mode register 0 (CSIM0) * Serial bus interface control register (SBIC) * Interrupt timing specify register (SINT) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. 296 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-3. Timer Clock Select Register 3 Format Symbol TCL3 7 1 6 0 5 0 4 0 3 2 1 0 Address FF43H After Reset 88H R/W R/W TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection Serial Clock in I2C Bus Mode MCS = 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 Setting prohibited fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.77 kHz) MCS = 0 fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.77 kHz) fXX/2 fXX/22 fXX/23 fXX/24 Serial Clock in 2-Wire or 3-Wire Serial I/O Mode MCS = 1 Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/210 (4.88 kHz) fXX/25 fX/211 (2.44 kHz) fXX/26 fX/212 (1.22 kHz) fXX/27 fX/213 (0.61 kHz) fXX/28 fXX/210 fX/210 (4.88 kHz) fXX/211 fX/211 (2.44 kHz) fXX/212 fX/212 (1.22 kHz) Setting prohibited Other than above Cautions 1. Set bit 4 to bit 6 to 0, and bit 7 to 1. 2. When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. fXX 2. fX : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency 3. MCS : Oscillation mode selection register bit 0 4. Figures in parentheses apply to operation with fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Figure 16-4. Serial Operating Mode Register 0 Format Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/WNote 1 CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection Input Clock to SCK0/SCL pin from off-chip 8-bit timer register 2 (TM2) output Note2 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) 0 1 1 x 0 1 R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 Operation Mode 3-wire serial l/O mode Start Bit MSB LSB SI0/SB0/SDA0/ SO0/SB1/SDA1/ P25 Pin Function P26 Pin Function SI0 Note3 (Input) SO0 (CMOS output) SB1/SDA1 (N-ch open-drain input/output) P26 (CMOS input/output) SCK0/SCL/P27 Pin Function SCK0 (CMOS input/output) 0 x 0 1 0 Note3 Note3 1 x 0 0 0 1 Note4 Note4 x x 0 0 0 1 1 1 Note4 Note4 1 0 0 x x 0 2-wire serial l/O mode or 2 1 I C Bus Mode P25 (CMOS input/output) MSB SB0/SDA0 (N-ch open-drain input/output) SCK0/SCL (N-ch open-drain input/output) R/W WUP 0 1 Wake-up Function Control Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition (when CMDD = 1) matches the slave address register data in I2C bus mode R COI 0 1 Slave Address Comparison Result Flag Note5 Slave address register not equal to serial I/O shift register 0 data Slave address register equal to serial I/O shift register 0 data R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled Notes 1. 2. 3. 4. 5. Remark Bit 6 (COI) is a read-only bit. I2C bus mode, the clock frequency becomes 1/16 of that output from TO2. Can be used as P25 (CMOS input/output) when used only for transmission. Can be used freely as port function. When CSIE0 = 0, COI becomes 0. x : don't care 298 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 16-5. Serial Bus Interface Control Register Format (1/2) Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H After Reset 00H R/W R/WNote BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W RELT Used for stop condition signal output. When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W CMDT Used for start condition signal output. When CMDT = 1, SO Iatch is cleared to (0). After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R RELD Stop Condition Detection Set Conditions (RELD =1) Clear Conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied * When stop condition signal is detected R CMDD Start Condition Detection Set Conditions (CMDD = 1) Clear Conditions (CMDD = 0) * When transfer start instruction is executed * When stop condition signal is detected * When CSIE0 = 0 * When RESET input is applied * When start condition signal is detected R/W ACKT Used to generate the ACK signal by software when 8-clock wait mode is selected. Keeps SDA0 (SDA1) low from set instruction (ACKT=1) execution to the next falling edge of SCL. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0. Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits. User's Manual U10105EJ4V1UM00 299 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-5. Serial Bus Interface Control Register Format (2/2) R/W ACKE 0 1 Acknowledge Signal Output Control Note1 Disables acknowledge signal automatic output. (However, output with ACKT is enabled) Used for reception when 8-clock wait mode is selected or for transmission. Note2 Enables acknowledge signal automatic output. Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output. Used in reception with 9-clock wait mode selected. R ACKD Acknowledge Detection Set Conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of SCL clock after completion of transfer Clear Conditions (ACKD = 0) * While executing the transfer start instruction * When CSIE0 = 0 * When RESET input is applied R/W Note3 BSYE 0 1 Control of N-ch Open-Drain Output for Transmission in I2C Bus Mode Output enabled (transmission) Output disabled (reception) Note4 Notes 1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT. 3. The busy mode can be canceled by start of serial interface transfer or reception of address signal. However, the BSYE flag is not cleared to 0. 4. When using the wake-up function, be sure to set BSYE to 1. 300 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 16-6. Interrupt Timing Specify Register Format (1/2) Symbol SINT 7 0 6 CLD 5 SIC 4 3 2 1 0 Address FF63H After Reset 00H R/W R/WNote 1 SVAM CLC WREL WAT1 WAT0 R/W WAT1 WAT0 0 0 Wait and Interrupt Control Generates interrupt service request at rising edge of 8th SCK0 clock cycle. (keeping clock output in high impedance) Setting prohibited Used in I2C bus mode. (8-clock wait) Generates interrupt service request at rising edge of 8th SCK0 clock cycle. (In the case of master device, makes SCL output low to enter wait state after 8 clock pulses are output. In the case of slave device, makes SCL output low to request wait state after 8 clock pulses are input.) Used in I2C bus mode. (9-clock wait) Generates interrupt service request at rising edge of 9th SCK0 clock cycle. (In the case of master device, makes SCL output low to enter wait state after 9 clock pulses are output. In the case of slave device, makes SCL output low to request wait state after 9 clock pulses are input.) 0 1 1 0 1 1 R/W WREL Wait Sate Cancellation Control 0 1 Wait state has been cancelled. Cancels wait state. Automatically cleared to 0 when the state is cancelled. (Used to cancel wait state by means of WAT0 and WAT1.) R/W CLC 0 Clock Level Control Note2 Used in I2C bus mode. Make output level of SCL pin low unless serial transfer is being performed. Used in I2C bus mode. Make SCL pin enter high-impedance state unless serial transfer is being performed. (except for clock line which is kept high) Used to enable master device to generate start condition and stop condition signals. 1 Notes 1. Bit 6 (CLD) is a read-only bit. 2. When not using the I2C mode, set CLC to 0. User's Manual U10105EJ4V1UM00 301 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-6. Interrupt Timing Specify Register Format (2/2) R/W SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 R/W SIC 0 1 INTCSI0 Interrupt Cause Selection Note1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer R CLD 0 1 SCK0/SCL Pin LevelNote2 Low level High level Notes 1. When using wake-up function in the I2C mode, set SIC to 1. 2. When CSIE0 = 0, CLD becomes 0. Remark SVA : Slave address register 302 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * I2C (Inter IC) bus mode 16.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. The serial I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register. In the operation stop mode, the P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 and P27/SCK0/SCL pins can be used as general input/output ports. (1) Register setting The operation stop mode is set with the serial operating mode register 0 (CSIM0). CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. The shaded area is used in the operation stop mode. Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/W CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled User's Manual U10105EJ4V1UM00 303 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0). (1) Register setting The 3-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0) and serial bus interface control register (SBIC). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. The shaded area is used in the 3-wire serial I/O mode. Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/WNote 1 CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) 0 1 1 x 0 1 R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 Note 2 Note 2 Operation Mode 3-wire serial l/O mode Start Bit MSB LSB SIO/SB0/SDA0 SO0/SB1/SDA1 /P25 Pin Function /P26 Pin Function SI0 (Input) Note 2 SCK0/SCL/P27 Pin Function SCK0 (CMOS input/output) 0 x 0 1 1 x 0 0 0 1 SO0 (CMOS output) 1 1 2-wire serial I/O mode (See section 16.4.3, "2-wire serial I/O mode operation".) or I2C bus mode (See section 16.4.4, "I2C bus mode operation".) R/W WUP 0 1 Wake-up Function Control Note 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition (when CMDD=1) matches the slave address register data in I2C bus mode R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as P25 (CMOS input/output) when used only for transmission. 3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected. Remark x : don't care 304 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the 3-wire serial I/O mode. Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H After Reset 00H R/W R/W BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W RELT When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W CMDT When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. User's Manual U10105EJ4V1UM00 305 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the SI0 pin is latched in SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 16-7. 3-Wire Serial I/O Mode Timings SCK0 1 2 3 4 5 6 7 8 SI0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CSIIF0 End of Transfer Transfer Start at the Falling Edge of SCK0 The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status can be manipulated by setting the RELT and CMDT bits. However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 16.4.6 SCK0/SCL/P27 pin output manipulation). (3) Other signals Figure 16-8 shows RELT and CMDT operations. Figure 16-8. RELT and CMDT Operations SO0 latch RELT CMDT 306 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register 0 (CSIM0). Figure 16-9. Circuit of Switching in Transfer Bit Order 7 6 Internal Bus 1 0 LSB-first MSB-first Read/Write Gate Read/Write Gate SO0 Latch SI0 Shift Register 0 (SIO0) D Q SO0 SCK0 Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (5) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1. * Internal serial clock is stopped or SCK0 is a high level after 8-bit serial transfer. Caution If CSIE0 is set to "1" after data write to SIO0, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. User's Manual U10105EJ4V1UM00 307 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.4.3 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 16-10. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode VDD VDD Master Slave SCK0 SCK0 SB0 (SB1) SB0 (SB1) (1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). 308 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. The shaded area is used in the 2-wire serial I/O mode. Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/WNote 1 CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) 0 1 1 x 0 1 R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 Operation Mode Start Bit SIO/SB0/SDA0 SO0/SB1/SDA1 /P25 Pin Function /P26 Pin Function SCK0/SCL/P27 Pin Function 0 x 3-wire Serial I/O mode (See Section 16.4.2, "3-wire serial I/O mode operation" Note 2 Note 2 0 1 1 x x 0 0 0 1 Note 2 Note 2 2-wire serial l/O mode or I2C bus mode P25 (CMOS input/output MSB SB0/SDA0 (N-ch open-drain input/output) SB1/SDA1 (N-ch open-drain input/output) SCK0/SCL (N-ch open-drain input/output) 1 0 0 x x 0 1 P26 (CMOS input/output) R/W WUP 0 1 Wake-up Function Control Note 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition (when CMDD=1) matches the slave address register data in I2C bus mode R COI 0 1 Slave Address Comparison Result FlagNote4 Slave address register not equal to serial I/O shift register 0 data Slave address register equal to serial I/O shift register 0 data R/W CSIE0 0 1 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used freely as port function. 3. Be sure to set WUP to 0 when the 2-wire serial I/O mode. 4. When CSIE0=0, COI becomes 0. Remark x : don't care User's Manual U10105EJ4V1UM00 309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the 2-wire serial I/O mode. Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H After Reset 00H R/W R/W BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W RELT When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W CMDT When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. 310 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. The shaded area is used in the 2-wire serial I/O mode. Symbol SINT 7 0 6 CLD 5 SIC 4 3 2 1 0 Address FF63H After Reset 00H R/W R/WNote 1 SVAM CLC WREL WAT1 WAT0 R/W SIC 0 1 INTCSI0 Interrupt Factor Selection CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon stop condition detection or termination of serial interface channel 0 transfer R CLD 0 1 SCK0 Pin LevelNote 2 Low level High level Notes 1. Bit 6 (CLD) is a read-only bit. 2. When CSIE0 = 0, CLD becomes 0. Caution Be sure to set bit 0 to bit 3 to 0 when 2-wire serial I/O mode is used. User's Manual U10105EJ4V1UM00 311 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/SDA0/P25 (or SB1/SDA1/P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into the shift register at the rising edge of SCK0. Upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 16-11. 2-Wire Serial I/O Mode Timings SCK0 1 2 3 4 5 6 7 8 SB0 (SB1) D7 D6 D5 D4 D3 D2 D1 D0 CSIIF0 End of Transfer Transfer Start at the Falling Edge of SCK0 The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain input/output and thus it must be externally connected to a pull-up resistor. Because it is necessary to turn off the N-ch transistor for data reception, write FFH to SIO0 in advance. The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be manipulated by setting the RELT and CMDT bits. However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 16.4.6 SCK0/SCL/P27 pin output manipulation). 312 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (3) Other signals Figure 16-12 shows RELT and CMDT operations. Figure 16-12. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch transistor must be turned off for data reception, write FFH to SIO0 in advance. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. (5) Error detection In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, SIO0. Thus, transmit error can be detected in the following way. (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred. (b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged to have occurred. User's Manual U10105EJ4V1UM00 313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.4.4 I2C bus mode operation The I2C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data bus (SDA0 or SDA1) line. Consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port pins and on-board wires. In the I2C bus specification, the master sends start condition, data, and stop condition signals to slave devices through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware. This simplifies I2C bus control sections in the application program. An example of a serial bus configuration is shown in Figure 16-13. This system below is composed of CPUs and peripheral ICs having serial interface hardware that complies with the I2C bus specification. Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because opendrain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the I2C bus. The signals used in the I2C bus mode are described in Table 16-4. Figure 16-13. Example of Serial Bus Configuration Using I2C Bus VDD VDD Master CPU Serial clock Serial data bus Slave CPU1 SCL SDA0(SDA1) SCL SDA0(SDA1) Slave CPU2 SCL SDA0(SDA1) Slave IC SCL SDA 314 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (1) I2C bus mode functions In the I2C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus. (b) Chip selection by specifying device addresses The master device can select a specific slave device connected to the I2C bus and communicate with it by sending in advance the address data corresponding to the destination device. (c) Wake-up function When address data is sent from the master device, slave devices compare it with the value registered in their internal slave address registers. If the values in one of the slave devices match, the slave device internally generates an interrupt signal to terminate the current processing and communicates with the master device. Therefore, CPUs other than the selected slave device on the I2C bus can perform independent operations during the serial communication. (d) Acknowledge signal (ACK) control function The master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally. (e) Wait signal (WAIT) control function When a slave device is preparing for data transmission or reception and requires more waiting time, the slave device outputs a wait signal on the bus to inform the master device of the wait status. (2) I2C bus definition This section describes the format of serial data communications and functions of the signals used in the I2C bus mode. First, the transfer timings of the start condition, data, and stop condition signals, which are output onto the signal data bus of the I2C bus, are shown in Figure 16-14. Figure 16-14. I2C Bus Serial Data Transfer Timing SCL 1-7 8 9 1-7 8 9 1-7 8 9 SDA0(SDA1) Start Address condition R/W ACK Data ACK Data ACK Stop condition The start condition, slave address, and stop condition signals are output by the master. The acknowledge signal (ACK) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent). A serial clock (SCL) is continuously supplied from the master device. User's Manual U10105EJ4V1UM00 315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer. See section 16.4.5, "Cautions on Use of I2C Bus Mode," for details of the start condition output. The start condition signal is detected by hardware incorporated in slave devices. Figure 16-15. Start Condition H SCL SDA0(SDA1) (b) Address The 7 bits following the start condition signal are defined as an address. The 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line. Each slave device on the bus line must therefore have a different address. Therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the data of the slave address register (SVA). After the comparison, only the slave device in which the data are a match becomes the communication partner, and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal. Figure 16-16. Address SCL 1 2 3 4 5 6 7 SDA0(SDA1) A6 A5 A4 A3 A2 A1 A0 R/W Address (c) Transfer direction specification The 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the transfer direction specification bit. If this bit is 0, it is the master device which will send data to the slave. If it is 1, it is the slave device which will send data to the master. Figure 16-17. Transfer Direction Specification SCL 1 2 3 4 5 6 7 8 SDA0(SDA1) A6 A5 A4 A3 A2 A1 A0 R/W Transfer direction specification 316 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer. In principle, the receiving side device returns an acknowledge signal to the sending device each time it receives 8-bit data. The only exception is when the receiving side is the master device and the 8-bit data is the last transfer data; the master device outputs no acknowledge signal in this case. The sending side that has tranferred 8-bit data waits for the acknowledge signal which will be sent from the receiving side. If the sending side device receives the acknowledge signal, which means a successful data transfer, it proceeds to the next processing. If this signal is not sent back from the slave device, this means that the data sent has not been received by the slave device, and therefore the master device outputs a stop condition signal to terminate subsequent transmissions. Figure 16-18. Acknowledge Signal SCL 1 2 3 4 5 6 7 8 9 SDA0iSDA1 j A6 A5 A4 A3 A2 A1 A0 R/W ACK (e) Stop condition If the SDA0 (SDA1) pin level changes from low to high while the SCL pin is high, this transition is defined as a stop condition signal. The stop condition signal is output from the master to the slave device to terminate a serial transfer. The stop condition signal is detected by hardware incorporated in the slave device. Figure 16-19. Stop Condition H SCL SDA0(SDA1) User's Manual U10105EJ4V1UM00 317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers. When the wait state is released, the master device can start the next transfer. For the releasing operation of slave devices, see section 16.4.5, "Cautions on Use of I2C Bus Mode." Figure 16-20. Wait Signal (a) Wait of 8 Clock Cycles Set low because slave device drives low, though master device returns to Hi-Z state. No wait is inserted after 9th clock cycle. (and before master device starts next transfer.) SCL of master device SCL of slave device 6 7 8 9 1 2 3 4 SCL SDA0(SDA1) D2 D1 D0 ACK D7 D6 D5 D4 Output by manipulating ACKT (b) Wait of 9 Clock Cycles Set low because slave device drives low, though master device returns to Hi-Z state. SCL of master device SCL of slave device SCL 6 7 8 9 1 2 3 SDA0(SDA1) D2 D1 D0 ACK D7 D6 D5 Output based on the value set in ACKE in advance 318 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (3) Register setting The I2C mode setting is performed by the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets 00H. The CSIM0 format is shown below, where the bits used in the I2C bus mode are shaded. Symbol 7 6 COI 5 WUP 4 3 2 1 0 Address FF60H After Reset 00H R/W R/W Note 1 CSIM0 CSIE0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W CSIM01 CSIM00 0 1 1 x 0 1 Serial Interface Channel 0 Clock Selection Input clock from off-chip to SCL pin 8-bit timer register 2 (TM2) output Note 2 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) PM26 P26 PM27 P27 Operation mode Start bit SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/P27 P25 pin function P26 pin function pin function P25 (CMOS I/O) SB0/SDA0 (N-ch opendrain I/O) SB1/SDA1 (N-ch opendrain I/O) P26 (CMOS I/O) SCK0/SCL (N-ch opendrain I/O) SCK0/SCL (N-ch opendrain I/O) R/W CSIM CSIM 04 03 0 1 x 1 CSIM PM25 P25 02 0 3-wire serial I/O mode (see section 16.4.2 "3-wire serial I/O mode operation") x x 0 Note3 Note3 0 0 0 0 1 2-wire MSB serial I/O or I2C bus mode 2-wire MSB serial I/O or I2C bus mode 1 1 1 x x 0 Note3 Note3 1 R/W WUP 0 1 Wake-up Function Control Interrupt request signal generation with each serial transfer in any mode In I2C bus mode, interrupt request signal is generated when the address data received after start condition detection (when CMDD = 1) matches data in slave address register. Slave Address Comparison Result Flag Note 4 Slave address register not equal to data in serial I/O shift register 0 Slave address register equal to data in serial I/O shift register 0 Serial Interface Channel 0 Operation Control Stops operation. Enables operation. R COI 0 1 R/W CSIE0 0 1 Notes 1. Bit 6 (COI) is a read-only bit. 2. In the I2C bus mode, the clock frequency is 1/16 of the clock frequency output by TO2. 3. Can be used freely as a port. 4. When CSIE0 = 0, COI is 0. Remark: x: Don't care User's Manual U10105EJ4V1UM00 319 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The SBIC format is shown below, where the bits used in the I2C bus mode are shaded. Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H After Reset 00H R/W R/WNote 1 BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W R RELT CMDT RELD 0 Use for stop condition output. When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. Use for start condition output. When CMDT = 1, SO latch is cleared to 0. After clearing SO latch, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. Stop Condition Detection Clear Conditions * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied Setting Condition * When stop condition is detected Start Condition Detection Clear Conditions * When transfer start instruction is executed * When stop condition is detected * When CSIE0 = 0 * When RESET input is applied Setting Condition * When start condition is detected SDA0 (SDA1) is set to low after the Set instruction execution (ACKT = 1) before the next SCL falling edge. Used for generating an ACK signal by software if the 8-clock wait mode is selected. Cleared to 0 if CSIE0 = 0 when a transfer by the serial interface is started. Acknowledge Signal Automatic Output Control Note 2 Disabled (with ACKT enabled). Used when receiving data in the 8-clock wait mode or when transmitting dataNote 3. Enabled. After completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of SCL clock (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output. Used for reception when the 9-clock wait mode is selected. Acknowledge Detection Clear Conditions * When transfer start instruction is executed * When CSIE0 = 0 * When RESET input is applied Set Conditions * When acknowledge signal is detected at the rising edge of SCL clock after completion of transfer Control of N-ch Open-Drain Output for Transmission in I2C Bus Mode Note 5 Output enabled (transmission) Output disabled (reception) 1 R CMDD 0 1 R/W ACKT R/W ACKE 0 1 R ACKD 0 1 R/W Note 4 BSYE 0 1 Notes 1. Bits 2, 3, and 6 (RELD, CMDD, ACKD) are read-only bits. 2. This setting must be performed prior to transfer start. 3. In the 8-clock wait mode, use ACKT for output of the acknowledge signal after normal data reception. 4. The busy mode can be released by the start of a serial interface transfer or reception of an address signal. However, the BSYE flag is not cleared. 5. When using the wake-up function, be sure to set BSYE to 1. 320 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. The SINT format is shown below, where the bits used in the I2C bus mode are shaded. Symbol SINT 7 0 6 CLD 5 SIC 4 3 2 1 0 Address FF63H After Reset 00H R/W R/WNote 1 SVAM CLC WREL WAT1 WAT0 R/W WAT1 0 0 1 WAT0 0 1 0 Interrupt control by wait Note 2 Interrupt service request is generated on rise of 8th SCK0 clock cycle (clock output is high impedance). Setting prohibited Used in I2C bus mode (8-clock wait) Generates an interrupt service request on rise of 8th SCL clock cycle. (In case of master device, SCL pin is driven low after output of 8 clock cycles, to enter the wait state. In case of slave device, SCL pin is driven low after input of 8 clock cycles, to require the wait state.) Used in I2C bus mode (9-clock wait) Generates an interrupt service request on rise of 9th SCL clock cycle. (In case of master device, SCL pin is driven low after output of 9 clock cycles, to enter the wait state. In case of slave device, SCL pin is driven low after input of 9 clock cycles, to require the wait state.) 1 1 R/W WREL 0 1 Wait release control Indicates that the wait state has been released. Releases the wait state. Automatically cleared to 0 after releasing the wait state. This bit is used to release the wait state set by means of WAT0 and WAT1. Clock level control Used in I2C bus mode. In cases other than serial transfer, SCL pin output is driven low. Used in I2C bus mode. In cases other than serial transfer, SCL pin output is set to high impedance. (Clock line is held high.) Used by master device to generate the start condition and stop condition signals. SVA bits used as slave address Bits 0 to 7 Bits 1 to 7 INTCSI0 interrupt source selection Note 3 CSIIF0 is set to 1 after end of serial interface channel 0 transfer. CSIIF0 is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected. SCL pin level Note 4 Low level High level R/W CLC 0 1 R/W SVAM 0 1 R/W SIC 0 1 R CLD 0 1 Notes 1. Bit 6 (CLD) is read-only. 2. When the I2C bus mode is used, be sure to set 1 and 0, or 1 and 1 in WAT0 and WAT1, respectively. 3. When using the wake-up function in I2C mode, be sure to set SIC to 1. 4. When CSIE0 = 0, CLD is 0. Remark SVA: Slave address register User's Manual U10105EJ4V1UM00 321 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (4) Various signals A list of signals in the I2C bus mode is given in Table 16-4. Table 16-4. Signals in I2C Bus Mode Signal name Start condition Description Definition : Function : Signaled by : SDA0 (SDA1) falling edge when SCL is high Note 1 Indicates that serial communication starts and subsequent data are address data. Master Signaled when : CMDT is set. Affected flag(s) : CMDD (is set.) Stop condition Definition : Function : Signaled by : Signaled when : Acknowledge signal (ACK) SDA0 (SDA1) rising edge when SCL is high Note 1 Indicates end of serial transmission. Master RELT is set. Affected flag(s) : RELD (is set) and CMDD (is cleared) Definition : Low level of SDA0(SDA1) pin during one SCL clock cycle after serial reception Function : Signaled by : Signaled when : Indicates completion of reception of 1 byte. Master or slave ACKT is set with ACKE = 1. Low-level signal output to SCL Indicates state in which serial reception is not possible. Slave WAT1, WAT0 = 1x. Synchronization clock for output of various signals Serial communication synchronization signal. Master See Note 2 below. 7-bit data synchronized with SCL immediately after start condition signal Indicates address value for specification of slave on serial bus. Master See Note 2 below. 1-bit data output in synchronization with SCL after address output Indicates whether data transmission or reception is to be performed. Master See Note 2 below. 8-bit data synchronized with SCL, not immediately after start condition Contains data actually to be sent. Master or slave Affected flag(s) : ACKD (is set.) Wait (WAIT) Definition : Function : Signaled by : Signaled when : Serial Clock (SCL) Definition : Function : Signaled by : Signaled when : Address (A6 to A0) Definition : Function : Signaled by : Signaled when : Transfer direction (R/W) Definition : Function : Signaled by : Signaled when : Data (D7 to D0)) Definition : Function : Signaled by : Affected flag(s) : None Affected flag(s) : CSIIF0. Also see Note 3 below. Affected flag(s) : CSIIF0. Also see Note 3 below. Affected flag(s) : CSIIF0. Also see Note 3 below. Signaled when : See Note 2 below. Affected flag(s) : CSIIF0. Also see Note 3 below. Notes 1. The level of the serial clock can be controlled by CLC of SINT. 2. Execution of instruction to write data to SIO0 when CSIE0 = 1 (serial transfer start directive). In the wait state, the serial transfer operation will be started after the wait state is released. 3. If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle of SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th clock cycle of SCL. If WUP = 1, CSIIF0 is set only when an address is received and the address matches the slave address register (SVA) value. 322 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (5) Pin configurations The configurations of the serial clock pin (SCL) and the serial data bus pins (SDA0, SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin. <1> Master .... N-ch open-drain output <2> Slave ....... Schmitt input (b) SDA0 (SDA1) Serial data input/output dual-function pin. Uses N-ch open-drain output and Schmitt-input buffers for both master and slave devices. Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because opendrain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the I2C bus. Figure 16-21. Pin Configuration VDD Master device SCL Clock output (Clock input) SDA0(SDA1) Data output Data input SDA0(SDA1) Data output Data input VDD SCL (Clock output) Clock input Slave devices Caution Because the N-ch open-drain output must be disabled during data reception, set BSYE of SBIC to 1 before writing FFH to SIO0. (6) Address match detection method In the I2C mode, the master can select a specific slave device by sending slave address data. Address match detection is performed automatically by the slave device hardware. A slave device address has a slave register (SVA), and compares its contents and the slave address sent from the master device. If they match and the wake-up function specification (WUP) bit is then 1, interrupt request flag (CSIIF0) is set. Caution Be sure to set the WUP bit to 1 before the master device sends slave address data to slave devices. Each slave device recognizes whether the slave device is selected or not by master device by comparing the content of the SVA register (which is in each slave device) and the slave address data, which is sent by master device immediately after the start condition signal. Only if the WUP bit has been set to 1 when they match, the slave device generates INTCSI0 signal. User's Manual U10105EJ4V1UM00 323 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (7) Error detection In the I2C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the SIO0 register of the transmitting device. (a) Comparison of SIO0 data before and after transmission In this case, a transmission error is judged to have occurred if the two data values are different. (b) Using the slave address register (SVA) Transmit data is set in SIO0 and SVA before transmission is performed. After transmission, the COI bit (match signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1" indicates normal transmission, and "0" indicates a transmission error. (8) Communication operation In the I2C bus mode, the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus. After the slave address data, the master sends the R/W bit which indicates the data transfer direction, and starts serial communication with the selected slave device. Data communication timing charts are shown in Figures 16-22 and 16-23. In the transmitting device, the shift register (SIO0) shifts transmission data to the SO latch in synchronization with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSB-first basis from the SDA0 or SDA1 pin to the receiving device. In the receiving device, the data input from the SDA0 or SDA1 pin is taken into the shift register (SIO0) in synchronization with the rising edge of SCL. (9) Start of transfer A serial transfer is started by setting transfer data in SIO0 if the following two conditions have been satisfied: (a) The serial interface channel 0 operation control bit (CSIE0) = 1. (b) After an 8-bit serial transfer, the internal serial clock is stopped or SCL is low. Cautions 1. Be sure to set CSIE0 to 1 before writing data in SIO0. Setting CSIE0 to 1 after writing data in SIO0 does not initiate transfer operation. 2. Because the N-ch open-drain output must be disabled during data reception, set BSYE of SBIC to 1 before writing FFH to SIO0. 3. If data is written to SIO0 while the slave is in the wait state, that data is held. The transfer is started when SCL is output after the wait state is cleared. When an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (CSIIF0) is set. 324 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Address Master device operation SIO0 Address SIO0 Data Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0(SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 H H L L L L H L L L L H L L L L 1 2 3 4 5 6 7 8 9 D7 1 2 3 4 5 A6 A5 A4 A3 A2 A1 A0 W ACK D6 D5 D4 SIO0 FFH User's Manual U10105EJ4V1UM00 325 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-22. Data Transmission from Master to Slave (b) Data (Both Master and Slave Selected 9-Clock Wait) (2 of 3) Master device operation SIO0 Data SIO0 Data Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0(SDA1) H L L L L L L L L L 1 D7 2 3 4 5 6 7 8 9 D7 1 2 3 4 5 6 7 8 D6 D5 D4 D3 D2 D1 D0 ACK D6 D5 D4 D3 D2 D1 Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 L H H L L L L H L SIO0 FFH SIO0 FFH 326 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-22. Data Transmission from Master to Slave (c) Stop Condition (Both Master and Slave Selected 9-Clock Wait) (3 of 3) Master device operation SIO0 Data SIO0 Address Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0(SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 H H L L L L H L L H L L L 1 D7 2 3 4 5 6 7 8 9 1 2 3 4 D6 D5 D4 D3 D2 D1 D0 ACK A6 A5 A4 SIO0 FFH SIO0 FFH SIO0 FFH User's Manual U10105EJ4V1UM00 327 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Address Master device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0(SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 L L L L H L SIO0 Data 1 2 3 4 5 6 7 8 9 1 2 3 4 5 L L L H L L SIO0 Address SIO0 FFH A6 A5 A4 A3 A2 A1 A0 R ACK D7 D6 D5 D4 328 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-23. Data Transmission from Slave to Master (b) Data (Both Master and Slave Selected 9-Clock Wait) (2 of 3) Master device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0(SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 L L L L L L L H L SIO0 Data SIO0 Data 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 H L H H L L L L L L SIO0 FFH SIO0 FFH D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 User's Manual U10105EJ4V1UM00 329 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) Figure 16-23. Data Transmission from Slave to Master (c) Stop Condition (Both Master and Slave Selected 9-Clock Wait) (3 of 3) Master device operation SIO0 FFH SIO0 Address Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0(SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 L L L L H L L H L 1 D7 2 3 4 5 6 7 8 9 1 2 3 4 D6 D5 D4 D3 D2 D1 D0 NAK A6 A5 A4 SIO0 Data SIO0 FFH SIO0 FFH 330 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.4.5 Cautions on use of I2C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal. Set 1 in CLC of SINT to drive the SCL pin high. After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output. If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is set to 1 after setting CLC to 1; a slave device may have set SCL to low (wait state). Figure 16-24. Start Condition Output SCL SDA0(SDA1) CLC CMDT CLD User's Manual U10105EJ4V1UM00 331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (2) Slave wait release (slave transmission) The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify register (SINT), or by executing an SIO0 write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line. Therefore, manipulate the P27 output latch through the program as shown in Figure 16-25 to transmit data correctly. At this time, control the low-level width ("a" in Figure 16-25) of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIO0 write instruction. In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is completed), set 1 in the WREL flag of SINT and release the wait. For these timings, see Figure 16-23. Figure 16-25. Slave Wait Release (Transmission) Master device operation Writing FFH to SIO0 Setting Setting ACKD CSIIF0 Software operation Hardware operation Serial reception Transfer line SCL 9 a1 2 3 SDA0(SDA1) A0 R ACK D7 D6 D5 Slave device operation Software operation P27 Write output data latch 0 to SIO0 P27 output latch 1 Hardware operation ACK Setting output CSIIF0 Wait release Serial transmission 332 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (3) Slave wait release (slave reception) The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify register (SINT), or by executing an SIO0 write instruction. When a slave receives data, if the SCL line immediately enters a high-impedance state due to a write to SIO0, the slave may not receive the first bit of the data sent from the master. This is because SIO0 cannot start operation if the SCL line is in a high-impedance state during execution of a write instruction to SIO0 (until the next instruction execution is started). Therefore, manipulate the P27 output latch through the program as shown in Figure 16-26 to receive data correctly. For these timings, see Figure 16-22. Figure 16-26. Slave Wait Release (Reception) Master device operation Writing data to SIO0 Setting Setting ACKD CSIIF0 * Software operation Hardware operation Serial transmission Transfer line SCL 9 1 2 3 SDA0(SDA1) A0 W ACK D7 D6 D5 Slave device operation Software operation P27 Write output FFH latch 0 to SIO0 P27 output latch 1 Hardware operation ACK Setting output CSIIF0 Wait release Serial reception (4) Reception completion of slave During processing of reception completion by a slave device, confirm the statuses of CMDD and COI (if CMDD = 1). This procedure is necessary to use the wake-up function normally. If an uncertain amount of data is sent from the master device, the slave device cannot determine whether the start condition signal or the data will be sent from the master. This may disable use of the wake-up function. User's Manual U10105EJ4V1UM00 333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) 16.4.6 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin enables static output by manipulating software in addition to normal serial clock output. The number of serial clocks can be set by software (SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the RELT and CMDT bits of serial bus interface control register (SBIC)). The SCK0/SCL/P27 pin output should be manipulated as described below. (1) In 3-wire serial I/O mode and 2-wire serial I/O mode The SCK0/SCL/P27 pin output level is manipulated by the P27 output latch. <1> Set serial operating mode register 0 (CSIM0) (SCK0 pin is set in the output mode and serial operation is enabled). While serial transfer is suspended, SCK0 is set to 1. <2> Manipulate the content of the P27 output latch by executing the bit manipulation instruction. Figure 16-27. SCK0/SCL/P27 Pin Configuration Set by bit manipulation instruction SCK0/SCL/P27 To Internal Circuit P27 Output Latch When CSIE0 = 1 and CSIM01 and CSIM00 are 1 and 0, or 1 and 1. SCK0 (1 when transfer stops) From Serial Clock Control Circuit 334 User's Manual U10105EJ4V1UM00 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78064Y Subseries) (2) In I2C bus mode The SCK0/SCL/P27 pin output level is manipulated by the CLC bit of interrupt timing specify register (SINT). <1> Set serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation is enabled). Set 1 to the P27 output latch. While serial transfer is suspended, SCL is set to 0. <2> Manipulate the content of the CLC bit of SINT by executing the bit manipulation instruction. Figure 16-28. SCK0/SCL/P27 Pin Configuration Set 1 SCK0/SCL/P27 To Internal Circuit P27 Output Latch When CSIE0 = 1 and CSIM01 and CSIM00 are 1 and 0, or 1 and 1. SCL Note From Serial Clock Control Circuit Note The level of SCL signal follows the contents of logic circuit shown in Figure 16-29. Figure 16-29. Logic Circuit of SCL Signal CLC (Set by bit manipulation instruction) SCL Wait Request Signal Serial Clock (low level when transfer stops) Remarks 1. This figure shows the relationship of each signal, and does not show the internal circuit. 2. CLC : Bit 3 of interrupt timing specify register (SINT) User's Manual U10105EJ4V1UM00 335 [MEMO] 336 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 17.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption. (2) Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin. The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator. (3) 3-wire serial I/O mode (MSB-first/LSB-first switchable) In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK2), and serial data lines (SI2, SO2). In the 3-wire serial I/O mode, simultaneous transmission and reception is possible, increasing the data transfer processing speed. Either the MSB or LSB can be specified as the start bit for an 8-bit data serial transfer, allowing connection to devices using either as the start bit. The 3-wire serial I/O mode is useful for connection to peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X series, 78K series, 17K series, etc. User's Manual U10105EJ4V1UM00 337 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 17.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 17-1. Serial Interface Channel 2 Configuration Item Register Configuration Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Control register Serial operating mode register 2 (CSIM2) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) 338 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 Figure 17-1. Serial Interface Channel 2 Block Diagram Internal Bus * Asynchronous Serial Interface Status Register Receive Buffer Register (RXB/SIO2) PE FE OVE Direction Control Circuit Asynchronous Serial Interface Mode Register TXE RXE PS1 PS0 CL SL ISRM SCK Direction Control Circuit Receive Shift Register (RXS) Transmit Shift Register (TXS/SIO2) RxD/SI2/ P70 TxD/SO2/ P71 PM71 Reception Control Circuit PM72 ASCK/ SCK2/P72 INTSER INTSR/INTCSI2 ISRM Transmission Control Circuit SCK Output Control Circuit INTST Note Baud Rate Generator fxx-fxx/210 SCK CSCK CSIE2 TXE RXE 4 4 CSIE2 CSIM CSCK 22 MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0 Serial Operating Mode Register 2 Baud Rate Generator Control Register Internal Bus Note See Figure 17-2 for the baud rate generator configuration. User's Manual U10105EJ4V1UM00 339 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 Figure 17-2. Baud Rate Generator Block Diagram CSIE2 TXE Start Bit Sampling Clock Selector Selector 5-Bit Counter Selector Transmit Clock ASCK/SCK2/P72 Selector fxx-fxx/210 1/2 Match MDL0-MDL3 4 TPS0-TPS3 SCK CSCK Decoder Selector 4 Receive Clock 1/2 Match 5-Bit Counter 4 RXE Start Bit Detection TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register Internal Bus 340 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation. TXS is written to with an 8-bit memory manipulation instruction. It cannot be read. TXS value is FFH after RESET input. Caution TXS must not be written to during a transmit operation. TXS and the receive buffer register (RXB) are allocated to the same address, and when a read is performed, the value of RXB is read. (2) Receive shift register (RXS) This register is used to convert serial data input to the RxD pin to parallel data. When one byte of data is received, the receive data is transferred to the receive buffer register (RXB). RXS cannot be directly manipulated by a program. (3) Receive buffer register (RXB) This register holds receive data. Each time one byte of data is received, new receive data is transferred from the receive shift register (RXS). If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB, and the MSB of RXB is always set to 0. RXB is read with an 8-bit memory manipulation instruction. It cannot be written to. RXB value is FFH after RESET input. Caution RXB and the transmit shift register (TXS) are allocated to the same address, and when a write is performed, the value is written to TXS. (4) Transmission control circuit This circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data written in the transmit shift register (TXS) in accordance with the contents set in the asynchronous serial interface mode register (ASIM). (5) Reception control circuit This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface mode register (ASIM). It performs error checks for parity errors, etc., during a receive operation, and if an error is detected, sets a value in the asynchronous serial interface status register (ASIS) in accordance with the error contents. User's Manual U10105EJ4V1UM00 341 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 17.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. * Serial Operating Mode Register 2 (CSIM2) * Asynchronous Serial Interface Mode Register (ASIM) * Asynchronous Serial Interface Status Register (ASIS) * Baud Rate Generator Control Register (BRGC) (1) Serial operating mode register 2 (CSIM2) This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode. CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM2 to 00H. Figure 17-3. Serial Operating Mode Register 2 Format Symbol 7 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After Reset 00H R/W R/W CSIM2 CSIE2 CSIM CSCK 22 CSCK 0 1 Clock Selection in 3-wire Serial I/O Mode Input clock from off-chip to SCK2 pin Dedicated baud rate generator output CSIM22 First Bit Specification 0 1 MSB LSB CSIE2 0 1 Operation Control in 3-wire Serial I/O Mode Operation stopped Operation enabled Cautions 1. Ensure that bit 0 and bit 3 to bit 6 are set to 0. 2. When UART mode is selected, CSIM2 should be set to 00H. 342 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Figure 17-4. Asynchronous Serial Interface Mode Register Format Symbol ASIM 7 TXE 6 RXE 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 SCK Address FF70H After Reset 00H R/W R/W SCK 0 1 ISRM Clock Selection in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator outputNote Control of Reception Completion Interrupt in Case of Error Generation Reception completion interrupt generated in case of error generation Reception completion interrupt not generated in case of error generation Transmit Data Stop Bit Length Specification 1 bit 2 bits Character Length Specification 7 bits 8 bits PS0 0 1 0 1 Parity Bit Specification No Parity 0 parity always added in transmission No parity test in reception (parity error not generated) Odd parity Even parity 0 1 SL 0 1 CL 0 1 PS1 0 0 1 1 RXE 0 1 TXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled Transmit Operation Control Transmit operation stopped Transmit operation enabled Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port. Cautions 1. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. 2. The serial transmit/receive operation must be stopped before changing the operating mode. User's Manual U10105EJ4V1UM00 343 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 Table 17-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode PM70 P70 PM71 P71 PM72 P72 Start Shift P70/SI2 P71/SO2 P72/SCK2 Bit Clock /RxD Pin /TxD Pin /ASCK Pin TXE RXE SCK CSIE2 CSIM22 CSCK Functions Functions Functions ASIM CSIM2 0 0 x 0 x x x Note1 x Note1 x Note1 x Note1 x Note1 x Note1 -- -- P70 P71 P72 Other than above Setting prohibited (2) 3-wire Serial I/O Mode PM70 P70 PM71 P71 PM72 P72 Start Shift P70/SI2 P71/SO2 P72/SCK2 Bit Clock /RxD Pin /TxD Pin /ASCK Pin TXE RXE SCK CSIE2 CSIM22 CSCK Functions Functions Functions ASIM CSIM2 0 0 0 1 0 0 1 Note2 x Note2 0 1 1 x MSB External clock Internal clock LSB External clock Internal clock SI2 Note2 SO2 (CMOS output) SCK2 input 1 0 1 SCK2 output Note2 1 1 0 1 x SI2 SO2 (CMOS output) SCK2 input 1 0 1 SCK2 output Other than above Setting prohibited (3) Asynchronous Serial Interface Mode PM70 P70 PM71 P71 PM72 P72 Start Shift P70/SI2 P71/SO2 P72/SCK2 Bit Clock /RxD Pin /TxD Pin /ASCK Pin TXE RXE SCK CSIE2 CSIM22 CSCK Functions Functions Functions ASIM CSIM2 1 0 0 0 0 0 x Note1 x Note1 0 1 1 x LSB External clock Internal clock External clock Internal clock External clock Internal clock P70 TxD (CMOS output) ASCK input 1 Note1 Note1 x Note1 x Note1 0 0 0 1 x Note1 P72 0 1 0 1 x x x RxD P71 ASCK input 1 x Note1 x P72 1 1 0 0 0 0 1 x 0 1 1 x TxD (CMOS output) ASCK input 1 x Note1 x Note1 P72 Other than above Setting prohibited Notes 1. Can be used freely as port function. 2. Can be used as P70 (CMOS input/output) when only transmitter is used. Remark x: Don't care User's Manual U10105EJ4V1UM00 344 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with a 1-bit or 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of the ASIS are undefined. RESET input sets ASIS to 00H. Figure 17-5. Asynchronous Serial Interface Status Register Format Symbol ASIS 7 0 6 0 5 0 4 0 3 0 2 PE 1 FE 0 OVE Address FF71H After Reset 00H R/W R OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generatedNote 1 (When next receive operation is completed before data from receive buffer register is read) FE 0 1 Framing Error Flag Framing error not generated Framing error generatedNote 2 (When stop bit is not detected) PE 0 1 Parity Error Flag Parity error not generated Parity error generated (When transmit data parity does not match) Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read. 2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface mode register, only single stop bit detection is performed during reception. User's Manual U10105EJ4V1UM00 345 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 17-6. Baud Rate Generator Control Register Format (1/2) Symbol BRGC 7 6 5 4 3 2 1 0 Address FF73H After Reset 00H R/W R/W TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 fSCKNote 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- k Note Can only be used in 3-wire serial I/O mode. Remarks 1. fSCK 2. k : 5-bit counter source clock : Value set in MDL0 to MDL3 (0 k 14) 346 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 Figure 17-6. Baud Rate Generator Control Register Format (2/2) 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 MCS=1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fXX/210 fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/210 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (4.9 kHz) (5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) MCS=0 fX/211 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 (2.4 kHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) 11 1 2 3 4 5 6 7 8 9 10 n Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1. fX 2. fXX 4. n : : : Main system clock oscillation frequency Main system clock frequency (fX or fX/2) Oscillation mode selection register bit 0 Value set in TPS0 to TPS3 (1 n 11) 3. MCS : 5. Figures in parentheses apply to operation with fX=5.0 MHz User's Manual U10105EJ4V1UM00 347 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system clock. The baud rate generated from the main system clock is found from the following expression. [Baud rate] = fXX 2n x (k+16) [Hz] fX fXX n k : Main system clock oscillation frequency : Main system clock frequency (fx or fx/2) : Value set in TPS0 to TPS3 (1 n 11) : Value set in MDL0 to MDL3 (0 k 14) Table 17-3. Relation between Main System Clock and Baud Rate fx=5.0 MHz MCS=1 MCS=0 MCS=1 fx=4.19 MHz MCS=0 Error (%) BRGC Set Value Error (%) 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 1.14 EBH E3H DBH CBH BBH ABH 9BH 8BH 7BH 6BH 61H 5BH -- 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 -- Baud Rate (bps) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value 75 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 06H 00H E0H D0H C0H B0H A0H 90H 80H 74H 70H 60H - 0.88 1.73 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 00H E6H E0H D0H C0H B0H A0H 90H 80H 70H 64H 60H 50H 1.73 0.88 1.73 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 0BH 03H EBH DBH CBH BBH ABH 9BH 8BH 7BH 71H 6BH 5BH * 76800 Remark MCS: Oscillation mode selection register bit 0 348 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = fASCK 2 x (k+16) fASCK k : : [Hz] Frequency of clock input to ASCK pin Value set in MDL0 to MDL3 (0 k 14) Table 17-4. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) Baud Rate (bps) 75 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 ASCK Pin Input Frequency 2.4 kHz 3.52 kHz 4.8 kHz 9.6 kHz 19.2 kHz 38.4 kHz 76.8 kHz 153.6 kHz 307.2 kHz 614.4 kHz 1000.0 kHz 1228.8 kHz User's Manual U10105EJ4V1UM00 349 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 17.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode 17.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced. In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK pins can be used as normal input/ output ports. (1) Register setting Operation stop mode settings are performed using serial operating mode register 2 (CSIM2) and the asynchronous serial interface mode register (ASIM). (a) Serial operating mode register 2 (CSIM2) CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM2 to 00H. The bit used in the operation stop mode is indicated by shading. Symbol 7 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After Reset 00H R/W R/W CSIM2 CSIE2 CSIM CSCK 22 CSIE2 0 1 Operation Control in 3-wire Serial I/O Mode Operation stopped Operation enabled Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0. 350 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. The bits used in the operation stop mode are indicated by shading. Symbol ASIM 7 TXE 6 RXE 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 SCK Address FF70H After Reset 00H R/W R/W RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled User's Manual U10105EJ4V1UM00 351 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 17.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin. The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator. (1) Register setting UART mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial interface mode register (ASIM), the asynchronous serial interface status register (ASIS), and the baud rate generator control register (BRGC). (a) Serial operating mode register 2 (CSIM2) CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM2 to 00H. The bits used in the UART mode are indicated by shading. When the UART mode is selected, 00H should be set in CSIM2. Symbol 7 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After Reset 00H R/W R/W CSIM2 CSIE2 CSIM CSCK 22 CSCK 0 1 Clock Selection in 3-wire Serial I/O Mode Input clock from off-chip to SCK2 pin Dedicated baud rate generator output CSIM22 First Bit Specification 0 1 MSB LSB CSIE2 0 1 Operation Control in 3-wire Serial I/O Mode Operation stopped Operation enabled Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0. 352 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. The bits used in the UART mode are indicated by shading. Symbol ASIM 7 TXE 6 RXE 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 SCK Address FF70H After Reset 00H R/W R/W SCK 0 1 Clock Selection in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator outputNote ISRM Control of Reception Completion Interrupt in Case of Error Generation Reception completion interrupt generated in case of error generation Reception completion interrupt not generated in case of error generation 0 1 SL 0 1 Transmit Data Stop Bit Length Specification 1 bit 2 bits CL 0 1 Character Length Specification 7 bits 8 bits PS1 0 0 1 1 PS0 0 1 0 1 Parity Bit Specification No Parity 0 parity always added in transmission No parity test in reception (parity error not generated) Odd parity Even parity RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port. Caution The serial transmit/receive operation must be stopped before changing the operating mode. User's Manual U10105EJ4V1UM00 353 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. The bits used in the UART mode are indicated by shading. Symbol ASIS 7 0 6 0 5 0 4 0 3 0 2 PE 1 FE 0 OVE Address FF71H After Reset 00H R/W R OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generatedNote 1 (When next receive operation is completed before data from receive buffer register is read) FE 0 1 Framing Error Flag Framing error not generated Framing error generatedNote 2 (When stop bit is not detected) PE 0 1 Parity Error Flag Parity error not generated Parity error generated (When transmit data parity does not match) Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read. 2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface mode register, only single stop bit detection is performed during reception. 354 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. The bits used in the UART mode are indicated by shading. Symbol BRGC 7 6 5 4 3 2 1 0 Address FF73H After Reset 00H R/W R/W TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 k (continued) Remark fSCK : 5-bit counter source clock k : Value set in MDL0 to MDL3 (0 k 14) User's Manual U10105EJ4V1UM00 355 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 MCS=1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fXX/210 fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fX/210 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (4.9 kHz) (5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) MCS=0 fX/211 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 (2.4 kHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) 11 1 2 3 4 5 6 7 8 9 10 n Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1. fX 2. fXX 4. n : Main system clock oscillation frequency : Main system clock frequency (fX or fX/2) : Value set in TPS0 to TPS3 (1 n 11) 3. MCS : Oscillation mode selection register bit 0 5. Figures in parentheses apply to operation with fX = 5.0 MHz. 356 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system clock. The baud rate generated from the main system clock is obtained with the following expression. [Baud rate] = fXX 2n x (k+16) [Hz] fX fXX n k : Main system clock oscillation frequency : Main system clock frequency (fx or fx/2) : Value set in TPS0 to TPS3 (1 n 11) : Value set in MDL0 to MDL3 (0 k 14) Table 17-5. Relation between Main System Clock and Baud Rate fx=5.0 MHz MCS=1 MCS=0 MCS=1 fx=4.19 MHz MCS=0 Error (%) BRGC Set Value Error (%) 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 1.14 EBH E3H DBH CBH BBH ABH 9BH 8BH 7BH 6BH 61H 5BH -- 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 -- Baud Rate (bps) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value 75 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 76800 06H 00H E0H D0H C0H B0H A0H 90H 80H 74H 70H 60H - 0.88 1.73 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 00H E6H E0H D0H C0H B0H A0H 90H 80H 70H 64H 60H 50H 1.73 0.88 1.73 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 0BH 03H EBH DBH CBH BBH ABH 9BH 8BH 7BH 71H 6BH 5BH Remark MCS: Oscillation mode selection register bit 0 * User's Manual U10105EJ4V1UM00 357 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = fASCK k fASCK 2 x (k+16) : : [Hz] Frequency of clock input to ASCK pin Value set in MDL0 to MDL3 (0 k 14) Table 17-6. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) Baud Rate (bps) 75 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 ASCK Pin Input Frequency 2.4 kHz 3.52 kHz 4.8 kHz 9.6 kHz 19.2 kHz 38.4 kHz 76.8 kHz 153.6 kHz 307.2 kHz 614.4 kHz 1000.0 kHz 1228.8 kHz 358 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 17-7. One data frame consists of a start bit, character bits, parity bit and stop bit(s). The specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out with asynchronous serial interface mode register (ASIM). Figure 17-7. Asynchronous Serial Interface Transmit/Receive Data Format One Data Frame Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit * Start bits ................. * Character bits ......... * Parity bits ................ * Stop bit(s) ................ 1 bit 7 bits/8 bits Even parity/odd parity/0 parity/no parity 1 bit/2 bits When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". The serial transfer rate is selected by means of the asynchronous serial interface mode register and the baud rate generator control register. If a serial data receive error is generated, the receive error contents can be determined by reading the status of the asynchronous serial interface status register (ASIS). * User's Manual U10105EJ4V1UM00 359 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected. (i) Even parity * At transmission Control is executed so that the number of bits with a value of "1" contained in the transmit data including parity bit is an even number. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data : 1 The number of bits with a value of "1" is an even number in transmit data : 0 * At reception The number of bits with a value of "1" contained in the receive data including parity bit are counted, and if this is an odd number, a parity error is generated. (ii) Odd parity * At transmission Conversely to the situation with even parity, control is executed so that the number of bits with a value of "1" contained in the transmit data including parity bit is an odd number. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data : 0 The number of bits with a value of "1" is an even number in transmit data : 1 * At reception The number of bits with a value of "1" contained in the receive data including parity bit are counted, and if this is an even number, a parity error is generated. (iii) 0 Parity When transmitting, the parity bit is set to "0" irrespective of the transmit data. At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective of whether the parity bit is set to "0" or "1". (iv) No parity A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error is not generated. 360 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt (INTST) is generated. Figure 17-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 STOP TxD (Output) START INTST D0 D1 D2 D6 D7 Parity (b) Stop bit length: 2 TxD (Output) START INTST D0 D1 D2 D6 D7 Parity STOP Caution Rewriting of the asynchronous serial interface mode register (ASIM) should not be performed during a transmit operation. If rewriting of the ASIM register is performed during transmission, subsequent transmit operations may not be possible (the normal state is restored by RESET input). It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (INTST) or the interrupt request flag (STIF) set by the INTST. User's Manual U10105EJ4V1UM00 361 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM. When the RxD pin input becomes low, the 5-bit counter starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output. If the RxD pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. When one frame of data has been received, the receive data in the shift register is transferred to the receive buffer register (RXB), and a reception completion interrupt (INTSR) is generated. If an error is generated, the receive data in which the error was generated is still transferred to RXB, and INTSR is generated. If the RXE bit is reset (0) during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB and ASIS are not changed, and INTSR and INTSER are not generated. Figure 17-9. Asynchronous Serial Interface Reception Completion Interrupt Timing STOP RxD (Input) START INTSR D0 D1 D2 D6 D7 Parity Caution The receive buffer register (RXB) must be read even if a receive error is generated. If RXB is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. 362 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in the asynchronous serial interface status register (ASIS) and at the same time a receive error interrupt (INTSER) is generated. Receive error causes are shown in Table 17-7. It is possible to determine what kind of error was generated during reception by reading the contents of the asynchronous serial interface status register (ASIS) in the reception error interrupt servicing (INTSER) (see Figures 17-9 and 17-10). The contents of ASIS are reset (0) by reading the receive buffer register (RXB) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). Table 17-7. Receive Error Causes Receive Errors Parity error Framing error Overrun error Cause Transmission-time parity specification and reception data parity do not match Stop bit not detected Reception of next data is completed before data is read from receive register buffer Figure 17-10. Receive Error Timing STOP RxD (Input) START INTSR D0 D1 D2 D6 D7 Parity INTSER Cautions 1. The contents of the ASIS register are reset (0) by reading the receive buffer register (RXB) or receiving the next data. To ascertain the error contents, ASIS must be read before reading RXB. 2. The receive buffer register (RXB) must be read even if a receive error is generated. If RXB is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. User's Manual U10105EJ4V1UM00 363 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared during transmission, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1 before executing the next transmission. (b) When bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is cleared during reception, receive buffer register (RXB) and receive completion interrupt (INTSR) are as follows. RxD Pin Parity RXB INTSR <1> <3> <2> When RXE is set to 0 at a time indicated by <1>, RXB holds the previous data and does not generate INTSR. When RXE is set to 0 at a time indicated by <2>, RXB renews the data and does not generate INTSR. When RXE is set to 0 at a time indicated by <3>, RXB renews the data and generates INTSR. 364 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 17.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X series, 78K series, 17K series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2). (1) Register setting 3-wire serial I/O mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial interface mode register (ASIM), and the baud rate generator control register (BRGC). (a) Serial operating mode register 2 (CSIM2) CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM2 to 00H. The bits used in the 3-wire serial I/O mode are indicated by shading. Symbol 7 6 0 5 0 4 0 3 0 2 1 0 0 * Address FF72H After Reset 00H R/W R/W CSIM2 CSIE2 CSIM CSCK 22 CSCK 0 1 Clock Selection in 3-wire Serial I/O Mode Input clock from off-chip to SCK2 pin Dedicated baud rate generator output CSIM22 First Bit Specification 0 1 MSB LSB CSIE2 0 1 Operation Control in 3-wire Serial I/O Mode Operation stopped Operation enabled Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0. User's Manual U10105EJ4V1UM00 365 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. The bits used in the 3-wire serial I/O mode are indicated by shading. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. Symbol ASIM 7 TXE 6 RXE 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 SCK Address FF70H After Reset 00H R/W R/W SCK 0 1 Clock Selection in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator output ISRM Control of Reception Completion Interrupt in Case of Error Generation Reception completion interrupt generated in case of error generation Reception completion interrupt not generated in case of error generation 0 1 SL 0 1 Transmit Data Stop Bit Length Specification 1 bit 2 bits CL 0 1 Character Length Specification 7 bits 8 bits PS1 0 0 1 1 PS0 0 1 0 1 Parity Bit Specification No Parity 0 parity always added in transmission No parity test in reception (parity error not generated) Odd parity Even parity RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled 366 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. The bits used in the UART mode are indicated by shading. Symbol BRGC 7 6 5 4 3 2 1 0 Address FF73H After Reset 00H R/W R/W TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 fSCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- k Remark fSCK : 5-bit counter source clock k : Value set in MDL0 to MDL3 (0 k 14) User's Manual U10105EJ4V1UM00 367 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 MCS=1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fXX/210 fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fX/210 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (4.9 kHz) (5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) MCS=0 fX/211 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 (2.4 kHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) 11 1 2 3 4 5 6 7 8 9 10 n Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1. fX 2. fXX 4. n : Main system clock oscillation frequency : Main system clock frequency (fX or fX/2) : Value set in TPS0 to TPS3 (1 n 11) 3. MCS : Oscillation mode selection register bit 0 5. Figures in parentheses apply to operation with fX = 5.0 MHz. 368 User's Manual U10105EJ4V1UM00 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC Setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0-TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1. The serial clock frequency becomes the same as the source clock frequency for the 5-bit counter. (ii) When the baud rate generator is used: Select a serial clock frequency with MDL0-MDL3 and TPS0-TPS3. Be sure then to set MDL0 to MDL3 to a value other than 1,1,1,1. The serial clock frequency is calculated by the following formula: fXX Serial clock frequency= [Hz] 2n x (k + 16) fX : fXX : n: k : Main system clock oscillation frequency Main system clock frequency (fX or fX/2) Value set in TPS0 to TPS3 (1 n 11) Value set in MDL0 to MDL3 (0 k 14) User's Manual U10105EJ4V1UM00 369 CHAPTER 17 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock (SCK2). Then transmit data is held in the SO2 latch and output from the SO2 pin. Also, receive data input to the SI2 pin is latched in the receive buffer register (RXB/SIO2) on the rise of SCK2. At the end of an 8-bit transfer, the operation of the transmit shift register (TXS/SIO2) or receive shift register (RXS) stops automatically, and the interrupt request flag (SRIF) is set. Figure 17-11. 3-Wire Serial I/O Mode Timing SCK2 1 2 3 4 5 6 7 8 SI2 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SRIF End of Transfer Transfer Start at the Falling Edge of SCK2 * (3) Transfer start Serial transfer is started by setting transfer data to the transmission shift register (TXS/SIO2) when the following two conditions are satisfied. * Serial interface channel 2 operation control bit (CSIE2) =1 * Internal serial clock is stopped or SCK2 is a high level after 8-bit serial transfer. Caution If CSIE2 is set to "1" after data write to TXS/SIO2, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (SRIF) is set. 370 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER 18.1 LCD Controller/Driver Functions The functions of the LCD controller/driver incorporated in the PD78064, 78064Y subseries are shown below. (1) Automatic output of segment signals and common signals is possible by automatic reading of the display data memory. (2) Any of five display modes can be selected. * Static * 1/2 duty (1/2 bias) * 1/3 duty (1/2 bias) * 1/3 duty (1/3 bias) * 1/4 duty (1/3 bias) (3) Any of four frame frequencies can be selected in each display mode. (4) Maximum of 40 segment signal outputs (S0 to S39); 4 common signal outputs (COM0 to COM3). Sixteen of the segment signal outputs can be switched to input/output ports in units of 2 (P80/S39 to P87/ S32, P90/S31 to P97/S24). (5) In mask ROM versions, split resistors for LCD drive voltage generation can be incorporated by mask option. (6) Operation on the subsystem clock is also possible. The maximum number of displayable pixels in each display mode is shown in Table 18-1. Table 18-1. Maximum Number of Display Pixels Bias Method - 1/2 Time Division Static 2 3 1/3 3 4 COM0-COM3 160 (40 segments x 4 commons) 4 Common Signals Used COM0 (COM1, 2, 3) COM0, COM1 COM0-COM2 Maximum Number of Pixels 40 (40 segments x 1 common) 80 (40 segments x 2 commons) 120 (40 segments x 3 commons) Note 1 2 3 Notes 1. 5 digits on 2. 10 digits on 3. 13 digits on 4. 20 digits on type LCD panel with 8 segments/digit. type LCD panel with 4 segments/digit. type LCD panel with 3 segments/digit. type LCD panel with 2 segments/digit. User's Manual U10105EJ4V1UM00 371 CHAPTER 18 LCD CONTROLLER/DRIVER 18.2 LCD Controller/Driver Configuration The LCD controller/driver is composed of the following hardware. Table 18-2. LCD Controller/Driver Configuration Item Display outputs Configuration Segment signals : 40 Dedicated segment signals: 24 Segment signal/input/output port dual function: 16 Common signals Control registers : 4 (COM0 to COM3) LCD display mode register (LCDM) LCD display control register (LCDC) Figure 18-1. LCD Controller/Driver Block Diagram Internal bus LCD display control register LCD LCD LCD LCD C7 C6 C5 C4 LEPS LIPS 4 2 Display data memory FA7FH FA7EH 7 6 54 321 0 7 6 54 321 0 FA68H FA67H FA66H 7 6 54 321 0 7 6 54 321 0 7 6 54 321 0 FA58H 7 6 54 321 0 LCD mode register LCD LCD LCD LCD LCD LCD LCD ON M6 M5 M4 M2 M1 M0 3 LCD clock selector f LCD 3 321 0 Note 1 321 0 Note 1 321 0 Note 1 321 0 Note 1 321 0 Note 1 321 0 Note 1 Timing controller Segment selector Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Common driver LCD drive voltage controller P98 output buffer P96 output buffer P80 output buffer S0 S1 S23 S24/P97 S25/P96 S39/P80 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 BIAS Notes 1. Selector 2. Segment driver 372 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-2. LCD Clock Select Circuit Block Diagram fXX/2 8 Selector fXT fW Prescaler Clear fW/2 6 Prescaler fLCD/2 fLCD/2 fLCD/2 fLCD 3 2 Selector LCDCL 3 TCL24 TMC21 LCDM6 LCDM5 LCDM4 LCD display mode register Timer clock select register 2 Watch timer mode control register Internal bus Remarks 1. The clock timer includes the circuit enclosed with the dotted line. 2. LCDCL : LCD clock 3. fLDC : LCD clock frequency User's Manual U10105EJ4V1UM00 373 CHAPTER 18 LCD CONTROLLER/DRIVER 18.3 LCD Controller/Driver Control Registers The LCD controller/driver is controlled by the following two registers. * * LCD display mode register (LCDM) LCD display control register (LCDC) (1) LCD display mode register (LCDM) This register sets display operation enabling/ disabling, the LCD clock, frame frequency, and display mode selection. LCDM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDM to 00H. Figure 18-3. LCD Display Mode Register Format Symbol 7 6 5 4 3 0 2 1 0 Address FFB0H State after reset 00H R/W R/W LCDM LCDON LCDM6 LCDM5 LCDM4 LCDM2 LCDM1 LCDM0 LCDM2 0 0 0 0 1 LCDM1 LCDM0 0 0 1 1 0 0 1 0 1 0 Number of Time Divisions 4 3 2 3 Static Setting prohibited LCD Clock Selection (See Note) fXX = 5.0 MHz Bias Method 1/3 1/3 1/2 1/2 Other than above LCDM5 0 0 0 0 LCDON 0 1 LCDM5 LCDM4 0 0 1 1 0 1 0 1 fXX = 4.19 MHz fW/29 fW/28 fW/26 (64 Hz) (128 Hz) (512 Hz) fXT = 32.768 kHz fW/29 (64 Hz) fW/28 (128 Hz) fW/27 (256 Hz) fW/26 (512 Hz) fW/29 fW/28 fW/26 (76 Hz) (153 Hz) (610 Hz) fW/27 (305 Hz) fW/27 (256 Hz) LCD Display Display on (All segment outputs signal non-selection.) Display off Note The LCD clock is supplied from the clock timer. When LCD display is performed, 1 should be set in bit 1 (TMC21) of the clock timer mode control register (TMC2). If TMC21 is reset to 0 during LCD display, the LCD clock supply will be stopped and the display will be disrupted. Remarks 1. fW 2. fXX 3. fX 4. fXT : Clock timer clock frequency (fXX/27 or fXT) : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency : Subsystem clock oscillation frequency 374 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER Table 18-3. Frame Frequencies (Hz) LCDCL Duty Static 1/2 1/3 1/4 fW/29 (64 Hz) 64 32 21 16 fW/28 (128 Hz) 128 64 43 32 fW/27 (256 Hz) 256 128 85 64 fW/26 (512 Hz) 512 256 171 128 Remarks 1. Figures in parentheses apply to operation with fX = 4.19 MHz or fXT = 32.768 kHz. 2. fW 3. fXX 4. fX 5. fXT : Clock timer clock frequency (fXX/27 or fXT) : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency : Subsystem clock oscillation frequency User's Manual U10105EJ4V1UM00 375 CHAPTER 18 LCD CONTROLLER/DRIVER (2) LCD display control register (LCDC) This register sets cut-off of the current flowing to split resistors for LCD drive voltage generation and switchover between segment output and input/output port functions. LCDC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC to 00H. Figure 18-4. LCD Display Control Register Format Symbol 7 6 5 4 3 0 2 0 1 LEPS 0 LIPS Address FFB2H State after reset 00H R/W R/W LCDC LCDC7 LCDC6 LCDC5 LCDC4 LEPS LIPS 0 0 1 0 1 0 LCD driving power supply selection Does not supply power to LCD. Supplies power to LCD from VDD pin. Supplies power to LCD from BIAS pin. (Shorts BIAS and VLC0 pins internally.) 1 1 Setting prohibited P80/S39-P97/S24 pin functions LCDC7 LCDC6 LCDC5 LCDC4 Port pins 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 P80-P97 P80-P95 P80-P93 P80-P91 P80-P87 P80-P85 P80-P83 P80-P81 None Segment pins None S24, S25 S24-S27 S24-S29 S24-S31 S24-S33 S24-S35 S24-S37 S24-S39 Other than above Setting prohibited Cautions 1. Pins which perform segment output cannot be used as output port pins even if 0 is set in the port register. 2. If a pin which performs segment output is read as a port, its value will be 0. 3. Pins set as segment outputs by LCDC cannot have an internal pull-up resistor connected regardless of the value of bits 0 and 1 (PUO8 and PUO9) of pull-up resistor option register H. 376 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER 18.4 LCD Controller/Driver Settings LCD controller/driver settings should be performed as shown below. When the LCD controller/driver is used, the clock timer should be set to the operational state beforehand. <1>Set "watch operation enabled" in timer clock selection register 2 (TCL2) and the clock timer mode control register (TMC2). <2>Set the initial value in the display data memory (FA58H to FA7FH). <3>Set the pins to be used as segment outputs in the LCD display control register (LCDC). <4>Set the display mode and LCD clock in the LCD display mode register (LCDM). Next, set data in the display data memory according to the display contents. User's Manual U10105EJ4V1UM00 377 CHAPTER 18 LCD CONTROLLER/DRIVER 18.5 LCD Display Data Memory The LCD display data memory is mapped onto addresses FA58H to FA7FH. The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller/driver. Figure 18-5 shows the relationship between the LCD display data memory contents and the segment outputs/ common outputs. Any area not used for display can be used as normal RAM. Figure 18-5. Relationship between LCD Display Data Memory Contents and Segment/Common Outputs Address FA7FH FA7EH FA7DH FA7CH b7 b6 b5 b4 b3 b2 b1 b0 S0 S1 S2 S3 FA5AH FA59H FA58H S37/P82 S38/P81 S39/P80 COM3 COM2 COM1 COM0 Caution The higher 4 bits of the LCD display data memory do not incorporate memory. Be sure to set them to 0. 378 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER 18.6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the LCD drive voltage VLCD). As an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals, it is driven by AC voltage. (1) Common signals For common signals, the selection timing order is as shown in Table 18-4 according to the number of time divisions set, and operations are repeated with these as the cycle. In the static mode, the same signal is output to COM0 through COM3. With 2-time-division operation, pins COM2 and COM3 are left open, and with 3-time-division operation, the COM3 pin is left open. Table 18-4. COM Signals COM signal COM0 Time division Static 2-time division 3-time division 4-time division Open Open Open COM1 COM2 COM3 (2) Segment signals Segment signals correspond to a 40-byte LCD display data memory (FA58H to FA7FH). Each display data memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the COM0, COM1, COM2 and COM3 timings respectively, and if the value of the bit is 1, it is converted to the selection voltage. If the value of the bit is 0, it is converted to the non-selection voltage and output to a segment pin (S0 to S39) (S24 to S39 have a dual function as input/output port pins). Consequently, it is necessary to check what combination of front surface electrodes (corresponding to the segment signals) and rear surface electrodes (corresponding to the common signals) of the LCD display to be used form the display pattern, and then write bit data corresponding on a one-to-one basis with the pattern to be displayed. In addition, because LCD display data memory bits 1 and 2 are not used with the static method, bits 2 and 3 are not used with the 2-time-division method, and bit 3 is not used with the 3-time-division method, these can be used for other than display purposes. Bits 4 to 7 are fixed at 0. User's Manual U10105EJ4V1UM00 379 CHAPTER 18 LCD CONTROLLER/DRIVER (3) Common signal and segment signal output waveforms The voltages shown in Table 18-5 are output in the common signals and segment signals. The VLCD ON voltage is only produced when the common signal and segment signal are both at the selection voltage; other combinations produce the OFF voltage. Table 18-5. LCD Drive Voltages (a) Static display mode Segment Common VLC0 , VSS Select VSS , VLC0 -VLCD , +VLCD Non-select VLC0 , VSS 0V,0V (b) 1/2 bias method Segment Common Select level Non-select level VLC0 , VSS VLC1=VLC2 Select VSS , VLC0 -VLCD , +VLCD -1/2VLCD , +1/2VLCD Non-select VLC0 , VSS 0V,0V +1/2VLCD , -1/2VLCD (c) 1/3 bias method Segment Common Select level Non-select level VLC0 , VSS VLC2 , VLC1 Select VSS , VLC0 -VLCD , +VLCD -1/3VLCD , +1/3VLCD Non-select VLC1 , VLC2 -1/3VLCD , +1/3VLCD -1/3VLCD , +1/3VLCD 380 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-6 shows the common signal waveform, and Figure 18-7 shows the common signal and segment signal voltages and phases. Figure 18-6. Common Signal Waveform (a) Static display mode VLC0 COMn (Static) VSS TF = T VLCD Remarks 1. T : One LCDCL cycle 2. T F : Frame frequency (b) 1/2 bias method VLC0 COMn VLC2 (Divided by 2) VSS TF = 2 x T VLC0 COMn VLC2 (Divided by 3) VSS TF = 3 x T VLCD VLCD Remarks 1. T : One LCDCL cycle 2. T F : Frame frequency (c) 1/3 bias method VLC0 COMn (Divided by 3) VLC1 VLC2 VSS TF = 3 x T VLC0 COMn (Divided by 4) VLC1 VLC2 VSS TF = 4 x T VLCD VLCD Remarks 1. T : One LCDCL cycle 2. T F : Frame frequency User's Manual U10105EJ4V1UM00 381 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-7. Common Signal and Static Signal Voltages and Phases (a) Static display mode Selected Not selected VLC0 Common signal VSS VLC0 Segment signal VSS T T VLCD VLCD Remark T : One LCDCL cycle (b) 1/2 bias method Selected Not selected VLC0 Common signal VLC2 VSS VLC0 Segment signal VLC2 VSS T T VLCD VLCD Remark T : One LCDCL cycle (c) 1/3 bias method Selected Not selected VLC0 Common signal VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS T T VLCD Segment signal VLCD Remark T : One LCDCL cycle 382 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER 18.7 Supply of LCD Drive Voltages VLC0, VLC1, VLC2 Split resistors for producing the LCD drive voltages can be incorporated in the PD78062, 78063, 78064, 78062Y, 78063Y, and 78064Y by mask option (the PD78P064, 78P064Y do not incorporate split resistors). Incorporating the split resistors makes it possible to produce LCD drive voltages appropriate to the various bias methods shown in Table 18-6 without using external split resistors. Also, an LCD drive voltage can be externally supplied from the BIAS pin to produce other LCD drive voltages. Table 18-6. LCD Drive Voltages (with On-Chip Split Resistor) Bias Method LCD Drive Voltage VLC0 VLC1 VLC2 VLCD 2/3VLCD 1/3VLCD VLCD 1/2VLCDNote VLCD 2/3VLCD 1/3VLCD No bias (static mode) 1/2 bias 1/3 bias Note With the 1/2 bias method, the VLC1 pin and VLC2 pin must be connected externally. Remarks 1. When the BIAS pin and VLC0 pin are open, VLCD = 3/5VDD (with onchip split resistor). 2. When the BIAS pin and VLC0 pin are connected, VLCD = VDD. Examples of internal supply of the LCD drive voltage in accordance with Table 18-6 are shown in Figures 188 and 18-9. An example of supply of the LCD drive voltage from off-chip is shown in Figure 18-10. Stepless LCD drive voltages can be supplied by means of variable resistor r. User's Manual U10105EJ4V1UM00 383 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-8. (a) LCD Drive Power Supply Connection Examples (with On-Chip Split Resistor) (b) 1/2 bias method mode (Example with VDD = 5 V, VLCD = 5 V) 1/3 bias method and static display mode (Example with VDD = 5 V, VLCD = 3 V) VDD VDD LIPS P-ch LIPS BIAS pin P-ch BIAS pin LEPS (= 0) VLC0 P-ch LEPS (= 0) P-ch 2R 2R VLC0 R VLC1 R VLC1 VLCD VLC2 R VLCD VLC2 R R VSS VSS R VLCD = 3/5VDD VLCD = VDD (c) 1/3 bias method and static display mode (Example with VDD = 5 V, VLCD = 5 V) VDD LIPS P-ch BIAS pin LEPS (= 0) VLC0 R VLC1 VLCD VLC2 R VSS R P-ch 2R VLCD = VDD 384 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-9. (a) LCD Drive Power Supply Connection Examples (with External Split Resistor) (b) Static display mode (Example with VDD = 5 V, VLCD = 3 V) Static display mode Note (Example with VDD = 5 V, VLCD = 5 V) VDD VDD LIPS P-ch BIAS pin LIPS P-ch BIAS pin LEPS (= 0) VLC0 P-ch LEPS (= 0) VLC0 P-ch 2R 3R VLC1 VLCD VLC2 VLCD VLC2 VLC1 VSS VSS VLCD = VDD VLCD = 3/5VDD Note LIPS should always be set to 1 (including in standby mode). (c) 1/2 bias method (Example with VDD = 5 V, VLCD = 3 V) (d) 1/3 bias method (Example with VDD = 5 V, VLCD = 3 V) VDD VDD LIPS P-ch BIAS pin LIPS P-ch BIAS pin LEPS (= 0) VLC0 P-ch 4R LEPS (= 0) VLC0 P-ch 2R 3R VLC1 VLCD VLC2 3R VSS VSS VLCD VLC2 VLC1 R R R VLCD = 3/5VDD VLCD = 3/5VDD User's Manual U10105EJ4V1UM00 385 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-10. Example of LCD Drive Voltage Supply from Off-Chip VDD VDD r LIPS (= 0) LEPS VLC0 P-ch BIAS pin P-ch R VLC1 VLCD VLC2 R VSS R VLCD = 3R VDD 3R + r 386 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER 18.8 18.8.1 Display Modes Static Display Example Figure 18-12 shows the connection of a static type 5-digit LCD panel with the display pattern shown in Figure 18-11 with the PD78064 subseries segment (S0 to S39) and common (COM0) signals. The display example is "123.45," and the display data memory contents (addresses FA58H to FA7FH) correspond to this. An explanation is given here taking the example of the third digit "3." ( 18-7 at the COM0 common signal timing. Table 18-7. Selection and Non-Selection Voltages (COM0) Segment Common COM0 S S S S NS S NS S S16 S17 S18 S19 S20 S21 S22 S23 ). In accordance with the display pattern in Figure 18-11, selection and non-selection voltages must be output to pins S16 through S23 as shown in Table S: Selection, NS: Non-selection From this, it can be seen that 10101111 must be prepared in the BIT0 bits of the display data memory (addresses FA68H to FA6FH) corresponding to S16 to S23. The LCD drive waveforms for S19, S20, and COM0 are shown in Figure 18-13. When S19 is at the selection voltage at the timing for selection with COM0, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Shorting the COM0 through COM3 lines increases the current drive capability because the same waveform as COM0 is output to COM1 through COM3. Figure 18-11. Static LCD Display Pattern and Electrode Connections S8n+3 S8n+4 S8n+2 S8n+5 COM0 S8n+6 S8n+1 S8n S8n+7 Remark n = 0 to 4 User's Manual U10105EJ4V1UM00 387 388 Data Memory Addresses Timing Strobes FA7FH 0 FA5FH 0 FA6FH FA58H C D C D A B E A B E 1 2 4 3 5 6 7 8 9 1 2 3 4 5 6 7 8 9 01 1 0 01 1 0 0 1 0 1 0 1 1 110 0 1 1 0 1 1 0 1 0 1 1 1 0 1 C D A S3 S1 S2 S7 S5 S6 S4 S8 S23 S21 S22 S20 S32 S31 S29 S30 S28 S27 S25 S26 S24 S19 S17 S18 S16 S15 S13 S14 S12 S11 S9 S10 B E 9 0 0 0 0 0 1 1 0 BIT0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BIT1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BIT2 CHAPTER 18 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BIT3 S0 COM0 COM2 COM1 COM3 S39 S37 S38 S36 S35 S33 S34 Figure 18-12. Static LCD Panel Connection Example User's Manual U10105EJ4V1UM00 LCD CONTROLLER/DRIVER Can be shorted. LCD Panel CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-13. Static LCD Drive Waveform Examples TF VLC0 COM0 VSS VLC0 S19 VSS VLC0 S20 VSS +VLCD COM0-S19 0 -VLCD +VLCD COM0-S20 0 -VLCD User's Manual U10105EJ4V1UM00 389 CHAPTER 18 LCD CONTROLLER/DRIVER 18.8.2 2-Time-Division Display Example Figure 18-15 shows the connection of a 2-time-division type 10-digit LCD panel with the display pattern shown in Figure 18-14 with the PD78064, 78064Y subseries segment signals (S0 to S39) and common signals (COM0, COM1). The display example is "123456.7890," and the display data memory contents (addresses FA58H to FA7FH) correspond to this. An explanation is given here taking the example of the eighth digit "3" ( ). In accordance with the display pattern in Figure 18-14, selection and non-selection voltages must be output to pins S28 through S31 as shown in Table 18-8 at the COM0 and COM1 common signal timings. Table 18-8. Selection and Non-Selection Voltages (COM0, COM1) Segment Common COM0 COM1 S NS S S NS S NS S S28 S29 S30 S31 S: Selection, NS: Non-selection From this, it can be seen that, for example, xx10 must be prepared in the display data memory (address FA80H) corresponding to S31. Examples of the LCD drive waveforms between S31 and the common signals are shown in Figure 18-16. When S31 is at the selection voltage at the COM1 selection timing, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Figure 18-14. 2-Time-Division LCD Display Pattern and Electrode Connections ,,,,, ,,,, , S4n + 2 S4n + 1 COM0 S4n + 3 Remark n = 0 to 9 ,,,,, ,, ,, S4n COM1 390 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-15. 2-Time-Division LCD Panel Connection Example Timing Strobes COM3 COM2 COM1 COM0 Open Open BIT0 BIT1 BIT2 BIT3 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX FA7FH E D C B A 9 8 7 6 5 4 3 2 1 1 0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 1 1 1 1 1 1 0 1 1 1 1 1 1 1 010 Data Memory Addresses FA6FH E D C B A 9 8 7 6 5 4 3 2 1 0 FA5FH E D C B A 9 FA58H 110 0 1 0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 1 0 1 0 1 1 1 10 1 0 00 1 0 1 1 1 0 Remark In bits marked X, 0 or 1 may be stored because this is a 2-time-division display. 0 0 0 0 0 1 1 1 01 1 1 00 0 1 0 1 1 1 0 LCD Panel 1 1 S17 S18 User's Manual U10105EJ4V1UM00 391 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-16. 2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) TF VLC0 COM0 VLC1(VLC2) VSS VLC0 COM1 VLC1(VLC2) VSS VLC0 S31 VLC1(VLC2) VSS VLCD +1/2VLCD COM0-S31 0 -1/2VLCD -VLCD +VLCD +1/2VLCD COM1-S31 0 -1/2VLCD -VLCD 392 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER 18.8.3 3-Time-Division Display Example Figure 18-18 shows the connection of a 3-time-division type 13-digit LCD panel with the display pattern shown in Figure 18-17 with the PD78064, 78064Y subseries segment signals (S0 to S38) and common signals (COM0 to COM2). The display example is "123456.7890123," and the display data memory contents (addresses FA59H to FA7FH) correspond to this. An explanation is given here taking the example of the eighth digit "6." ( in Table 18-9 at the COM0 to COM2 common signal timings. Table 18-9. Selection and Non-Selection Voltages (COM0 to COM2) Segment Common COM0 COM1 COM2 S: Selection, NS: Non-selection NS S S S S S S S -- S21 S22 S23 ). In accordance with the display pattern in Figure 18-17, selection and non-selection voltages must be output to pins S21 through S23 as shown From this, it can be seen that x110 must be prepared in the display data memory (address FA6AH) corresponding to S21. Examples of the LCD drive waveforms between S21 and the common signals are shown in Figure 18-19 (1/2 bias method) and Figure 18-20 (1/3 bias method). When S21 is at the selection voltage at the COM1 selection timing, and S21 is at the selection voltage at the COM2 selection timing, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Figure 18-17. 3-Time-Division LCD Display Pattern and Electrode Connections S3n + 1 COM0 S3n + 2 Remark n = 0 to 12 , , ,, , ,, , S3n ,,,, ,, ,,,, ,,,, COM1 COM2 User's Manual U10105EJ4V1UM00 393 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-18. 3-Time-Division LCD Panel Connection Example Timing Strobes COM3 COM2 COM1 COM0 1 BIT0 1 BIT1 0 BIT2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BIT3 Open FA7FH E D C B A 9 8 7 6 5 4 3 2 1 Data Memory Addresses S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 LCD Panel 1 0 1 1 0 1 0 0 1 1 1 1 1 1 111 1 0 0 1 111 0 1 1 1 0 1 1 0 FA6FH E D C B A 9 8 7 6 5 4 3 2 1 0 FA5FH E D C B A 9 FA58H 0 X' 1 0 X' 0 0 X' 1 0 X' 0 0 X' 1 0 X' 1 0 0 1 S17 1 1 1 0 1 1 0 1 1 01 1 1 01 1 1 0 1 0 0 0 1 1 01 1 0 0 1 1 0 1 0 11 0 1 1 1 0 1 Remarks 1. x' : Irrelevant bits because they have no corresponding segment in the LCD panel 2. x : Irrelevant bits because this is a 3-time-division display 394 User's Manual U10105EJ4V1UM00 X' 0 0 X' 1 0 X' 1 0 X' 0 0 X' 1 0 X' 1 1 X' 0 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-19. 3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) TF VLC0 COM0 VLC1(VLC2) VSS VLC0 COM1 VLC1(VLC2) VSS VLC0 COM2 VLC1(VLC2) VSS VLC0 S21 VLC1(VLC2) VSS +VLCD +1/2VLCD COM0-S21 0 -1/2VLCD -VLCD +VLCD +1/2VLCD COM1-S21 0 -1/2VLCD -VLCD +VLCD +1/2VLCD COM2-S21 0 -1/2VLCD -VLCD User's Manual U10105EJ4V1UM00 395 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-20. 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) TF VLC0 COM0 VLC1 VLC2 VSS VLC0 COM1 VLC1 VLC2 VSS VLC0 COM2 VLC1 VLC2 VSS VLC0 S21 VLC1 VLC2 VSS +VLCD +1/3VLCD COM0-S21 0 -1/3VLCD -VLCD +VLCD +1/3VLCD COM1-S21 0 -1/3VLCD -VLCD +VLCD +1/3VLCD COM2-S21 0 -1/3VLCD -VLCD 396 User's Manual U10105EJ4V1UM00 CHAPTER 18 LCD CONTROLLER/DRIVER 18.8.4 4-Time-Division Display Example Figure 18-22 shows the connection of a 4-time-division type 20-digit LCD panel with the display pattern shown in Figure 18-21 with the PD78064, 78064Y subseries segment signals (S0 to S39) and common signals (COM0 to COM3). The display example is "123456.78901234567890," and the display data memory contents (addresses FA58H to FA7FH) correspond to this. An explanation is given here taking the example of the 15th digit "6." ( 10 at the COM0 to COM3 common signal timings. Table 18-10. Selection and Non-Selection Voltages (COM0 to COM3) Segment Common COM0 COM1 COM2 COM3 S NS S S S S S S S28 S29 ). In accordance with the display pattern in Figure 18-21, selection and non-selection voltages must be output to pins S28 and S29 as shown in Table 18- S: Selection, NS: Non-selection From this, it can be seen that 1101 must be prepared in the display data memory (address FA63H) corresponding to S28. Examples of the LCD drive waveforms between S28 and the COM0 and COM1 signals are shown in Figure 1823 (for the sake of simplicity, waveforms for COM2 and COM3 have been omitted). When S28 is at the selection voltage at the COM0 selection timing, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Figure 18-21. 4-Time-Division LCD Display Pattern and Electrode Connections S2n Remark n = 0 to 18 ,,,,, ,, , ,,,, S2n + 1 COM0 COM2 ,, ,, ,, ,, COM1 COM3 User's Manual U10105EJ4V1UM00 397 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-22. 4-Time-Division LCD Panel Connection Example Timing Strobes COM3 COM2 COM1 COM0 BIT0 BIT1 BIT2 BIT3 FA7FH E D C B A 9 8 7 6 5 4 3 2 1 Data Memory Addresses 1 1 1 0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 LCD Panel 1 0 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 01 11 1 0 1 1 1 0 1 1 111 100 1 1 1 1 1 1 1 11 1 0 1 1 010 101 0 FA6FH E D C B A 9 8 7 6 5 4 3 2 1 0 FA5FH E D C B A 9 FA58H 0 0 0 1 01 0 0 0 1 0 0 0 1 S17 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 00 10 1 1 0 1 11 10 1 0 1 1 1 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 11 1 1 01 1 1 0 1 0 0 0 398 User's Manual U10105EJ4V1UM00 0 0 1 0 1 0 0 01 0 1 10 0 1 0 0 0 1 0 0 0 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-23. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) COM0 , , TF , , VLC0 VLC1 VLC2 VSS VLC0 COM1 VLC1 VLC2 VSS VLC0 COM2 VLC1 VLC2 VSS VLC0 COM3 VLC1 VLC2 VSS VLC0 S28 VLC1 VLC2 VSS +VLCD +1/3VLCD COM0-S28 0 -1/3VLCD -VLCD +VLCD +1/3VLCD COM1-S28 0 -1/3VLCD -VLCD User's Manual U10105EJ4V1UM00 399 [MEMO] 400 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally (that is, even in interrupt disabled state). It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal. One interrupt from the watchdog timer is incorporated as a non-maskable interrupt. (2) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (PR). Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same priority are simultaneously generated, each interrupts has a predetermined priority (see Table 19-1). A standby release signal is generated. Six external interrupts and 12 internal interrupts are incorporated as maskable interrupts. (3) Software interrupt This is a vectored interrupt to be generated by executing the BRK instruction. It is acknowledged even in interrupt disabled state. The software interrupt does not undergo interrupt priority control. User's Manual U10105EJ4V1UM00 401 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.2 Interrupt Sources and Configuration Twenty non-maskable, maskable, and software interrupts are provided as interrupt causes (see Table 19-1). Table 19-1. Interrupt Source List Maskability Default(Note1) Priority NonMaskable Maskable -- Name INTWDT Interrupt Source Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H End of serial interface channel 0 transfer Serial interface channel 2 UART reception error generation End of serial interface channel 2 UART reception End of serial interface channel 2 3-wire transfer End of serial interface channel 2 UART transfer Reference time interval signal from watch timer Generation of 16-bit timer register, capture/compare register (CR00) match signal Generation of 16-bit timer register, capture/compare register (CR01) match signal Generation of 8-bit timer/event counter 1 match signal Generation of 8 bit timer/event counter 2 match signal End of A/D converter conversion BRK instruction execution Internal 001CH Internal 0014H (B) Internal/ External Internal Vector Address 0004H Type (Note2) (A) 0 INTWDT (B) 1 2 3 4 5 6 7 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTCSI0 (C) (D) 8 INTSER 0018H 9 INTSR 001AH INTCSI2 10 INTST 11 12 INTTM3 001EH INTTM00 0020H 13 INTTM01 0022H 14 INTTM1 0024H 15 INTTM2 0026H 16 Software -- INTAD BRK 0028H 003EH (E) Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupts. 0 is the highest priority and 16 is the lowest priority. 2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 19-1. 402 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal Bus Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus MK IE PR ISP Interrupt Request IF Priority Control Circuit Vector Table Address Generator Standby Release Signal (C) External maskable interrupt (INTP0) Internal Bus Sampling Clock Select Register (SCS) External Interrupt Mode Register (INTM0) MK IE PR ISP Interrupt Request Sampling Clock Edge Detector IF Priority Control Circuit Vector Table Address Generator Standby Release Signal User's Manual U10105EJ4V1UM00 403 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) Internal Bus External Interrupt Mode Register (INTM0, INTM1) MK IE PR ISP Interrupt Request Edge Detector IF Priority Control Circuit Vector Table Address Generator Standby Release Signal (E) Software interrupt Internal Bus Interrupt Request Priority Control Circuit Vector Table Address Generator IF IE : : Interrupt request flag Interrupt enable flag Inservice priority flag Interrupt mask flag Priority specify flag ISP : MK : PR : 404 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L) * Interrupt mask flag register (MK0L, MK0H, MK1L) * Priority specify flag register (PR0L, PR0H, PR1L) * External interrupt mode register (INTM0, INTM1) * Sampling clock select register (SCS) * Program status word (PSW) Table 19-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources. Table 19-2. Various Flags Corresponding to Interrupt Request Sources Interrupt Request Signal Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTTM00 INTTM01 INTTM1 INTTM2 INTTM3 INTWDT INTCSI0 INTSR/INTCSI2 INTSER INTST INTAD Interrupt Request Flag PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 TMIF00 TMIF01 TMIF1 TMIF2 TMIF3 TMIF4 CSIIF0 SRIF SERIF STIF ADIF Interrupt Mask Flag PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 TMMK00 TMMK01 TMMK1 TMMK2 TMMK3 TMMK4 CSIMK0 SRMK SERMK STMK ADMK Priority Specify Flag PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 TMPR00 TMPR01 TMPR1 TMPR2 TMPR3 TMPR4 CSIPR0 SRPR SERPR STPR ADPR User's Manual U10105EJ4V1UM00 405 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register IF0 use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to 00H. Figure 19-2. Interrupt Request Flag Register Format Symbol IF0L 7 0 7 6 PIF5 6 5 PIF4 5 4 PIF3 4 3 PIF2 3 2 PIF1 2 1 0 Address FFE0H After Reset 00H R/W R/W PIF0 TMIF4 1 0 1 0 CSIIF0 0 IF0H TMIF01 TMIF00 TMIF3 STIF 7 IF1L WTIF Note SRIF SERIF 3 0 2 FFE1H 00H R/W 6 0 5 0 4 0 ADIF TMIF2 TMIF1 FFE2H 00H R/W x x IFx 0 1 Interrupt Request Flag No interrupt request signal Interrupt request signal is generated; Interrupt request state Note WTIF is test input flag. Vectored interrupt is not generated. Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0. 2. Because port 0 has a dual function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. Set always 0 in IF1L bits 3 through 6, IF0L bit 7, and IF0H bit 1. 406 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to FFH. Figure 19-3. Interrupt Mask Flag Register Format After Reset FFH Symbol MK0L 7 1 7 6 5 4 3 2 1 0 Address FFE4H R/W R/W PMK5 PMK4 PMK3 PMK2 PMK 6 5 4 3 2 PMK TMMK4 1 1 1 0 CSIMK0 0 MK0H TMMK01 TMMK00 TMMK3 STMK SRMK SERMK 7 MK1L WTMK Note FFE5H FFH R/W 6 1 5 1 4 1 3 1 2 ADMK TMMK2 TMMK1 FFE6H FFH R/W xxMKx 0 1 Interrupt Servicing Control Interrupt servicing enabled Interrupt servicing disabled Note WTMK controls standby mode release enable/disable. Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value becomes undefined. 2. Because port 0 has a dual function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. Set always 1 in MK1L bits 3 through 6, MK0L bit 7, and MK0H bit 1. User's Manual U10105EJ4V1UM00 407 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to FFH. Figure 19-4. Priority Specify Flag Register Format Symbol PR0L 7 1 7 6 5 4 3 2 1 0 Address FFE8H After Reset FFH R/W R/W PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 TMPR4 6 5 4 3 2 1 1 1 0 CSIPR0 0 PR0H TMPR01 TMPR00 TMPR3 STPR SRPR SERPR 7 PR1L 1 6 1 5 1 4 1 3 1 2 FFE9H FFH R/W ADPR TMPR2 TMPR1 FFEAH FFH R/W xxPRx 0 1 Priority Level Selection High priority level Low priority level Cautions 1. When a watchdog timer is used in watchdog timer mode 1, set 1 in TMPR4 flag. 2. Set always 1 in PR1L bits 3 through 7, PR0L bit 7, and PR0H bit 1. 408 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP0 to INTP5. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 19-5. External Interrupt Mode Register 0 Format Symbol 7 6 5 4 3 2 1 0 0 0 Address FFECH After Reset 00H R/W R/W INTM0 ES31 ES30 ES21 ES20 ES11 ES10 ES11 ES10 0 0 1 1 0 1 0 1 INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES21 ES20 0 0 1 1 0 1 0 1 INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES31 ES30 0 0 1 1 0 1 0 1 INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges User's Manual U10105EJ4V1UM00 409 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS Figure 19-6. External Interrupt Mode Register 1 Format After Reset 00H Symbol INTM1 7 0 6 0 5 4 3 2 1 0 Address FFEDH R/W R/W ES61 ES60 ES51 ES50 ES41 ES40 ES41 ES40 0 0 1 1 0 1 0 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 ES50 0 0 1 1 0 1 0 1 INTP4 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES61 ES60 0 0 1 1 0 1 0 1 INTP5 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges 410 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS (5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is removed with sampling clocks. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS to 00H. Figure 19-7. Sampling Clock Select Register Format Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF47H After Reset 00H R/W R/W SCS1 SCS0 INTP0 Sampling Clock Selection SCS1 SCS0 0 0 1 1 0 1 0 1 fxx/2 N 7 fx/2 (39.1 kHz) 5 fx/2 (156.3 kHz) 8 fx/2 (19.5 kHz) 6 fx/2 (78.1 kHz) MCS = 1 MCS = 0 fxx/27 fxx/25 fxx/2 6 fx/2 (78.1 kHz) 6 fx/2 (39.1 kHz) 7 Caution fXX/2N is a clock to be supplied to the CPU and fXX/25, fXX/26 and fXX/27 are clocks to be supplied to the peripheral hardware. fXX/2N stops in the HALT mode. Remarks 1. N 2. fXX 3. fX : : : Value (N=0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Oscillation mode selection register bit 0 4. MCS : 5. Values in parentheses when operated with fX = 5.0 MHz. User's Manual U10105EJ4V1UM00 411 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS When the INTP0 input level is active twice in succession, the noise remover sets PIF0 flag to 1. Figure 19-8. Noise Remover Input/Output Timing (during rising edge detection) (a) When input is less than the sampling cycle (tSMP) tSMP Sampling Clock INTP0 PIF0 "L" Because INTP0 level is not active twice in succession, PIF0 output remains at low level. (b) When input is equal to or twice the sampling cycle (tSMP) tSMP Sampling Clock INTP0 1 2 2 PIF0 Because INTP0 level is active twice in succession in 2 , PIF0 flag is set to 1. (c) When input is twice or more than the cycle frequency (tSMP) tSMP Sampling Clock INTP0 PIF0 Because INTP0 level is active two or more times in succession, PIF0 flag is set to 1. 412 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt servicing are mapped. Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI). When a vectored interrupt is acknowledged or the BRK instruction is executed, PSW is automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag. The acknowledged interrupt is also saved into the stack with the PUSH PSW instruction. It is reset from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets PSW to 02H. Figure 19-9. Program Status Word Format 7 PSW IE 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY State after Reset 02H Used when normal instruction is executed ISP 0 Priority of Interrupt Currently Being Received High-priority interrupt servicing (low-priority interrupt disable) Interrupt not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) 1 IE 0 1 Interrupt Acknowledge Enable/Disable Disable Enable User's Manual U10105EJ4V1UM00 413 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Non-maskable interrupt acknowledge operation A non-maskable interrupt is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, PSW and PC, in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched. A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. 414 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS Figure 19-10. Non-Maskable Interrupt Acknowledge Flowchart Start WDTM4=1 (with watchdog timer mode selected)? Yes No Interval timer Overflow in WDT? No Yes WDTM3=0 (with non-maskable interrupt selected)? No Reset processing Yes Interrupt request generation WDT interrupt servicing? No Interrupt request held pending Yes Interrupt control register unaccessed? No Yes Interrupt service start WDTM : Watchdog timer mode register WDT : Watchdog timer Figure 19-11. Non-Maskable Interrupt Acknowledge Timing PSW and PC Save, Jump to Interrupt Servicing CPU Instruction Instruction Instruction Interrupt Sevicing Program TMIF4 User's Manual U10105EJ4V1UM00 415 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS Figure 19-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request NMI Request 1 Instruction Execution NMI Request Reserve Reserved NMI Request Processing (b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine NMI Request 1 Instruction Execution NMI Request NMI Request Reserved Reserved Although two or more NMI requests have been generated, only one request has been acknowledged. 416 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.4.2 Maskable interrupt acknowledge operation A maskable interrupt becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt MK flag is cleared to 0. A vectored interrupt is acknowledged in an interrupt enable state (with IE flag set to 1). However, a low-priority interrupt is not acknowledged during high-priority interrupt service (with ISP flag reset to 0). Wait times maskable interrupt request generation to interrupt servicing are as follows. Table 19-3. Times from Maskable Interrupt Request Generation to Interrupt Service Minimum Time When xxPRx = 0 When xxPRx = 1 Note maximized. Remark 1 clock cycle = 1/CPU clock frequency (fCPU) If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. Two or more requests specified for the same priority, the default priorities apply. Any reserved interrupts are acknowledged when they become acknowledgeable. Figure 19-13 shows interrupt acknowledge algorithms. If a maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, PSW and PC, in that order, the IE flag is reset to 0, and the acknowledged interrupt priority specify flag contents are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded into PC and branched. Return from the interrupt is possible with the RETI instruction. 7 clock cycles 8 clock cycles Maximum Time Note 32 clock cycles 33 clock cycles If an interrupt request is generated just before a divide instruction, the wait time is User's Manual U10105EJ4V1UM00 417 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS Figure 19-13. Interrupt Acknowledge Processing Algorithm Start No x x IF=1? Yes (Interrupt Request Generation) No x x MK=0? Yes Interrupt request reserve Yes (High priority) x x PR=0? No (Low Priority) Yes Any highpriority interrupt among simultaneously generated xxPR=0 interrupts? No No Interrupt request reserve Any Simultaneously generated xxPR=0 interrupts? No Any Simultaneously generated high-priority interrupts? No Yes Interrupt request reserve IE=1? Yes Vectored interrupt servicing Yes Interrupt request reserve No Interrupt request reserve No Interrupt request reserve Interrupt request reserve IE=1? Yes ISP=1? Yes Vectored interrupt servicing 418 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS Figure 19-14. Interrupt Acknowledge Timing (Minimum Time) 6 Clocks PSW and PC Save, Jump to Interrupt Servicing Interrupt Servicing Program CPU Processing Instruction Divide Instruction x x IF (x x PR=1) 8 Clocks x x IF (x x PR=0) 7 Clocks Remark 1 clock cycle = 1/CPU clock frequency (fCPU) Figure 19-15. Interrupt Acknowledge Timing (Maximum Time) 25 Clocks 6 Clocks PSW and PC Save, Jump to Interrupt Servicing Interrupt Servicing Program CPU Processing Instruction Divide Instruction x x IF (x x PR=1) 33 Clocks x x IF (x x PR=0) 32 Clocks Remark 1 clock cycle = 1/CPU clock frequency (fCPU) User's Manual U10105EJ4V1UM00 419 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.4.3 Software interrupt acknowledge operation A software interrupt is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt is acknowledged, it is saved in the stacks, PSW and PC, in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into PC and branched. Return from the software interrupt is possible with the RETB instruction. Caution Do not use the RETI instruction for returning from the software interrupt. 19.4.4 Multiple interrupt servicing Multiple interrupts, in which another interrupt is acknowledged during execution of an interrupt, can be controlled by priorities. Two types of priority control are available; control in the order of default priority and programmable priority control by setting the priority specify flag registers (PR0L, PR0H and PR1L). In the former, if two or more interrupts are generated simultaneously, interrupt servicing is carried out in accordance with the priority (default priority) preassigned to each interrupt request (see Table 19-1). In the latter, interrupt requests are divided into a high-priority group and a low-priority group by setting the bits corresponding to PR0L, PR0H, and PR1L. The following are the interrupt requests enabled for multiple interrupts. Table 19-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Multiple Interrupt Non-maskable Request Interrupt Request D E E E IE=1 D E E E Maskable Interrupt Request PR=0 IE=0 D D D D IE=1 D D E E PR=1 IE=0 D D D D Interrupt being Acknowledged Non-maskable interrupt servicing Maskable interrupt servicing ISP=0 ISP=1 Software interrupt servicing Remarks 1. E 2. D : Multiple interrupt enable : Multiple interrupt disable 3. ISP and IE are the flags contained in PSW ISP=0 : An interrupt with higher priority is being serviced ISP=1 : An interrupt is not accepted or an interrupt with lower priority is being serviced IE=0 IE=1 : Interrupt acknowledge is disabled : Interrupt acknowledge is enabled 4. PR is a flag contained in PR0L, PR0H, PR1L PR=0 PR=1 : Higher priority level : Lower priority level 420 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS Figure 19-16. Multiple Interrupt Example Example 1 Main Processing INTxx Servicing IE=0 EI EI INTyy (PR=0) INTzz (PR=0) RETI IE=0 EI INTyy Servicing IE=0 INTzz Servicing INTxx (PR=1) RETI RETI Example 2 Main Processing INTxx Servicing INTyy Servicing EI IE=0 EI INTyy (PR=1) RETI INTxx (PR=0) IE=1 1 Instruction Execution IE=0 RETI Example 3 Main Processing INTxx Servicing IE=0 INTyy (PR=0) RETI INTyy Servicing EI INTxx (PR=0) 1 Instruction Execution IE=0 RETI User's Manual U10105EJ4V1UM00 421 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.4.5 Interrupt reserve Interrupt acknowledge is temporarily reserved between any of the following instructions and the next instruction to be executed. * MOV * MOV * MOV * MOV1 * MOV1 * AND1 * OR1 * XOR1 * SET1 * CLR1 * RETB * RETI * PUSH * POP PSW PSW PSW, #byte A, PSW PSW, A PSW.bit, CY CY, PSW.bit CY, PSW.bit CY, PSW.bit CY, PSW.bit PSW.bit PSW.bit * BT PSW.bit, $addr16 * BF PSW.bit, $addr16 * BTCLR * EI * DI * Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers Caution Because the IE flag is cleared to 0 by the software interrupt (by executing the BRK instruction), interrupts are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction. However, non-maskable interrupt requests are acknowledged. PSW.bit, $addr16 Figure 19-17. Interrupt Request Hold Save PSW and PC, Jump to interrupt service Interrupt service program CPU processing Instruction N Instruction M x x IF Remarks 1. Instruction N: Instruction that holds interrupts requests 2. Instruction M: Instructions other than interrupt request pending instruction 3. The xxPR values do not affect the operation of xxIF. 422 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.5 Test Functions Vector processing is not performed, but the test input flag is set to 1. In this function, the standby release signal is generated. There are two test input factors as shown in Table 19-5. The basic configuration is shown in Figure 19-18. Table 19-5. Test Input Factors Test Input Factors Name INTWT INTPT11 Trigger Watch timer overflow Falling edge detection at port 11 Internal/ External Internal External Figure 19-18. Basic Configuration of Test Function Internal bus MK Test input signal IF Standby release signal IF: test input flag MK: test mask flag 19.5.1 Registers controlling the test function The test function is controlled by the following three registers. * Interrupt request flag register 1L (IF1L) * Interrupt mask flag register 1L (MK1L) * Key return mode register (KRM) The names of the test input flags and test mask flags corresponding to the test input signals are listed in Table 19-6. Table 19-6. Flags Corresponding to Test Input Signals Test input signal name INTWT INTPT11 Test input flag WTIF KRIF Test mask flag WTMK KRMK User's Manual U10105EJ4V1UM00 423 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure 19-19. Format of Interrupt Request Flag Register 1L Symbol 7 6 0 5 0 4 0 3 0 2 1 0 Address FFE2H When Reset 00H R/W R/W IF1L WTIF ADIF TMIF2 TMIF1 WTIF 0 1 Watch timer overflow detection flag Not detected Detected Caution Be sure to set bits 3 through 6 to 0. (2) Interrupt mask flag register 1L (MK1L) It is used to set the standby mode enable/disable at the time the standby mode is released by the watch timer. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to FFH by the RESET signal input. Figure 19-20. Format of Interrupt Mask Flag Register 1L Symbol 7 6 1 5 1 4 0 3 0 2 1 0 Address FFE6H When Reset FFH R/W R/W MK1L WTMK ADMK TMMK2 TMMK1 WTMK 0 1 Standby mode control by watch timer Enables releasing the standby mode. Disables releasing the standby mode. Caution Be sure to set bits 3 through 6 to 1. 424 User's Manual U10105EJ4V1UM00 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 11 falling edge detection), and selects port 11 falling edge input. KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 19-21. Key Return Mode Register Format Symbol KRM 7 0 6 0 5 0 4 0 3 2 1 0 Address FFB8H When Reset 02H R/W R/W KRM3 KRM2 KRMK KRIF KRIF 0 1 KRMK 0 1 Not detected Key Return Signal Detected (port 11 falling edge detection) Standby Mode Control by Key Return Signal Standby mode release enabled Standby mode release disabled KRM3 KRM2 Selection of Port 11 Falling Edge Input 0 0 1 1 0 1 0 1 P117 P114-P117 P112-P117 P110-P117 Caution When port 11 falling edge detection is used, be sure to clear KRIF to 0 (not cleared to 0 automatically). User's Manual U10105EJ4V1UM00 425 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS 19.5.2 Test input signal acknowledge operation (1) Internal test signal If the watch timer overflows, the WTIF flag is set. The watch function is available by checking the WTIF flag at a shorter cycle than the watch timer overflow cycle. (2) External test signal When a falling edge is input to the port 4 (P110 to P117) pins, KRIF is set. If port 11 is used as key matrix return signal input, whether or not a key input has been applied can be checked from the KRIF status. 426 User's Manual U10105EJ4V1UM00 CHAPTER 20 STANDBY FUNCTION 20.1 Standby Function and Configuration 20.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in the STOP mode. The HALT mode is valid to restart immediately upon interrupt request and to carry out intermittent operations such as in watch applications. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops and the whole system stops. CPU current consumption can be considerably decreased. Data memory low-voltage hold (down to VDD = 1.8 V) is possible. Thus, the STOP mode is effective to hold data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request. In any mode, all the contents of the register, flag and data memory just before standby mode setting are held. The input/output port output latch and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). The HALT mode can be used with either the main system clock or the subsystem clock. 2. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation and execute the STOP instruction. 3. The following sequence is recommended for power consumption reduction of the A/D converter when the standby function is used: first clear bit 7 (CS) of ADM to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. * * User's Manual U10105EJ4V1UM00 427 CHAPTER 20 STANDBY FUNCTION 20.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it takes 217/fX, not 218/fX, until the STOP mode is cleared by RESET input. Figure 20-1. Oscillation Stabilization Time Select Register Format Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FFFAH After Reset 04H R/W R/W OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 12 14 Selection of Oscillation Stabilization Time when STOP Mode is Released MCS = 1 2 /fxx 2 /fx(819 s) 12 14 MCS = 0 2 /fx(1.64 ms) 15 2 /fx(6.55 ms) 13 2 /fxx 2 /fx(3.28 ms) 215/fxx 215/fx(6.55 ms) 216/fxx 216/fx(13.1 ms) 217/fxx 217/fx(26.2 ms) 216/fx(13.1 ms) 17 2 /fx(26.2 ms) 18 2 /fx(52.4 ms) Other than above Setting prohibited Caution The wait time after STOP mode clear does not include the time (see "a" in the illustration below) from STOP mode clear to clock oscillation start, regardless of clearance by RESET input or by interrupt generation. STOP Mode Clear X1 Pin Voltage Waveform a VSS Remarks 1. fXX 2. fX : Main system clock frequency (fX or fX/2) : Main system clock oscillation frequency 3. MCS : Oscillation mode select register bit 0 4. Values in parentheses apply to operating at fX = 5.0 MHz 428 User's Manual U10105EJ4V1UM00 CHAPTER 20 STANDBY FUNCTION 20.2 Standby Function Operations 20.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 20-1. HALT Mode Operating Status HALT mode setting HALT execution during main system clock operation w/ subsystem Item Clock Generator CPU Port (output latch) 16-bit timer/event counter clock (Note1) Operation stop. Status before HALT mode setting is held. Operable. Operable when watch timer output with fXT selected as count clock (fXT is selected as count clock for watch timer). 8-bit timer/event counter 1 and 2 Watch timer Operable. Operable if fXX/27 is selected as count clock. Watchdog timer A/D converter Serial Interface LCD controller/driver Operable. Operable. Operable Operable if fXX/27 is selected as count clock. External interrupt INTP1 to INTP5 INTP0 Operable when a clock (fXX/25, fXX/26, fXX/27) for the peripheral hardware is selected as sampling clock. Operable. Operation stops. Operable. Operable. Operation stops. Operable at external SCK. Operable if fXT is selected as count clock. Operable. Operablewhen TI1 or TI2 is selected as count clock. Operable if fXT is selected as count clock. w/o. subsystem clock (Note2) HALT execution during subsystem clock operation Main system Main system clock oscillates clock stops * Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops. Notes 1. Including case when external clock is supplied. 2. Including case when external clock is not supplied. User's Manual U10105EJ4V1UM00 429 CHAPTER 20 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction is executed. Figure 20-2. HALT Mode Clear upon Interrupt Generation HALT Instruction Standby Release Signal Operating Mode Wait HALT Mode Oscillation Wait Operating Mode Clock Remarks 1. The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. 2. Wait time will be as follows: * When vectored interrupt service is carried out: 8 to 9 clocks * When vectored interrupt service is not carried out: 2 to 3 clocks (b) Clear upon non-maskable interrupt request The HALT mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled. (c) Clear upon unmasked test input The HALT mode is cleared by unmasked test input and the next address instruction of the HALT instruction is executed. 430 User's Manual U10105EJ4V1UM00 CHAPTER 20 STANDBY FUNCTION (d) Clear upon RESET input As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 20-3. HALT Mode Release by RESET Input Wait (217/fx : 26.2 ms) HALT Instruction RESET Signal Operating Mode Reset Period Oscillation stop HALT Mode Oscillation Oscillation Stabilization Wait Status Oscillation Operating Mode Clock Remarks 1. fX : Main system clock oscillation frequency 2. Time value in parentheses is when fX = 5.0 MHz. Table 20-2. Operation after HALT Mode Release Release Source Maskable interrupt request MKxx 0 0 0 0 0 1 Non-maskable interrupt request Test input 0 1 RESET input - - - - x x x x x x Next address instruction execution HALT mode hold Reset processing - PRxx 0 0 1 1 1 x - IE 0 1 0 x 1 x x ISP x x 1 0 1 x x Interrupt service execution HALT mode hold Interrupt service execution Operation Next address instruction execution Interrupt service execution Next address instruction execution x: Don't care User's Manual U10105EJ4V1UM00 431 CHAPTER 20 STANDBY FUNCTION 20.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. * Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pull-up resistor to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait set using the oscillation stabilization time select register (OSTS), the operating mode is set. The operating status in the STOP mode is described below. * STOP mode setting Item Clock Generator CPU Port (output latch) 16-bit timer/event counter Table 20-3. STOP Mode Operating Status With subsystem clock Without subsystem clock Only main system clock stops oscillation. Operation stop. Status before STOP mode setting is held. Operable when watch timer output with fXT selected is selected as count clock (fXT is selected as count clock for watch timer). Operation stops. 8-bit timer/event counter 1 and 2 Watch timer Watchdog timer A/D converter Serial Interface LCD controller/driver External interrupt INTP0 INTP1 to INTP5 Other than UART UART Operable when TI1 and TI2 are selected for the count clock. Operable when fXT is selected for the count clock. Operation stops. Operation stops. Operable when externally supplied clock is specified as the serial clock. Operation stops. Operable when fXT is selected for the count clock. Operation is impossible. Operable. Operation stops. Operation stops. 432 User's Manual U10105EJ4V1UM00 CHAPTER 20 STANDBY FUNCTION (2) STOP mode release The STOP mode can be cleared with the following three types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt acknowledge is disabled, the next address instruction is executed. Figure 20-4. STOP Mode Release by Interrupt Generation Wait (Time set by OSTS) STOP Instruction Standby Release Signal Operationg Mode Oscillation STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Oscillation Operating Mode Clock Remark The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. (b) Release by unmasked test input The STOP mode is cleared by unmasked test input. After the lapse of oscillation stabilization time, the instruction at the next address of the STOP instruction is executed. User's Manual U10105EJ4V1UM00 433 CHAPTER 20 STANDBY FUNCTION (c) Release by RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 20-5. Release by STOP Mode RESET Input Wait (217/fx : 26.2 ms) STOP Instruction RESET Signal Operating Mode Oscillation Clock Reset Period STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Oscillation Operating Mode Remarks 1. fX : Main system clock oscillation frequency 2. Time value in parentheses is when fX = 5.0 MHz. Table 20-4. Operation after STOP Mode Release Release Source Maskable interrupt request MKxx 0 0 0 0 0 1 Test input 0 1 RESET input - PRxx 0 0 1 1 1 x - - - IE 0 1 0 x 1 x x x x ISP x x 1 0 1 x x x x Interrupt service execution STOP mode hold Next address instruction execution STOP mode hold Reset processing Operation Next address instruction execution Interrupt service execution Next address instruction execution x: Don't care 434 User's Manual U10105EJ4V1UM00 CHAPTER 21 RESET FUNCTION 21.1 Reset Function The following two operations are available to generate the reset signal. (1) (2) External reset input with RESET pin Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in Table 21-1. Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. When a high level is input to the RESET input, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (217/fX). The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (217/fX) (see Figure 21-2 to 214). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pin becomes high-impedance. Figure 21-1. Block Diagram of Reset Function RESET Reset Control Circuit Reset Signal Count Clock Watchdog Timer Stop Overflow Interrupt Function User's Manual U10105EJ4V1UM00 435 CHAPTER 21 RESET FUNCTION Figure 21-2. Timing of Reset Input by RESET Input X1 Normal Operation Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation (Reset Processing) RESET Internal Reset Signal Delay Delay Port Pin High Impedance Figure 21-3. Timing of Reset due to Watchdog Timer Overflow X1 Normal Operation Watchdog Timer Overflow Internal Reset Signal Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation (Reset Processing) Port Pin High Impedance Figure 21-4. Timing of Reset Input in STOP Mode by RESET Input X1 STOP Instruction Execution Stop Status (Oscillation Stop) Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation RESET Internal Reset Signal Normal Operation (Reset Processing) Delay Port Pin Delay High Impedance 436 User's Manual U10105EJ4V1UM00 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (1/2) Hardware Program counter (PC) Note1 Status after Reset The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Program status word (PSW) RAM Data memory General register Port (Output latch) Ports 0 to 3, Port 7 to 11 (P0-P3, P7-P11) Undefined 02H Undefined Note2 Undefined Note2 00H FFH 00H 04H 00H Note3 Port mode register (PM0 to PM3, PM5 to PM7, PM12, PM13) Pull-up resistor option register (PUOH, PUOL) Processor clock control register (PCC) Oscillation mode selection register (OSMS) Memory size switching register (IMS) Oscillation stabilization time select register (OSTS) 16-bit timer/event counter Timer register (TM0) Capture/compare register (CR00, CR01) Clock selection register (TCL0) Mode control register (TMC0) Capture/compare control register 0 (CRC0) Output control register (TOC0) 8-bit timer/event counter 1, 2 Timer register (TM1, TM2) Compare registers (CR10, CR20) Clock select register (TCL1) Mode control registers (TMC1) Output control register (TOC1) 04H 00H Undefined 00H 00H 04H 00H 00H Undefined 00H 00H 00H Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remains unchanged after reset. 2. The post-reset status is held in the standby mode. 3. The values after reset depend on the product. PD78062, 78062Y : 44H, PD78063, 78063Y : C6H, PD78064, 78064Y : C8H, PD78P064, 78P064Y : C8H User's Manual U10105EJ4V1UM00 437 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (2/2) Hardware Status after Reset 00H 00H 00H 88H Undefined 00H 00H Undefined 00H 00H 00H FFH * Watch timer Watchdog timer Serial interface Mode control register (TMC2) Clock select register (TCL2) Mode register (WDTM) Clock select register (TCL3) Shift registers (SIO0) Mode registers (CSIM0, CSIM2) Serial bus interface control register (SBIC) Slave address register (SVA) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Transmit shift register (TXS) Receive buffer register (RXB) Interrupt timing specify register (SINT) 00H 01H Undefined 00H 00H 00H 00H FFH FFH 00H 02H 00H A/D converter Mode register (ADM) Conversion result register (ADCR) Input select register (ADIS) LCD controller/driver Display mode register (LCDM) Display control register (LCDC) Interrupt Request flag register (IF0L, IF0H, IF1L) Mask flag register (MK0L, MK0H, MK1L) Priority specify flag register (PR0L, PR0H, PR1L) External interrupt mode register (INTM0, INTM1) Key return mode register (KRM) Sampling clock select register (SCS) 438 User's Manual U10105EJ4V1UM00 CHAPTER 22 PD78P064, 78P064Y The PD78P064, 78P064Y replace the internal mask ROM of the PD78064, 78064Y with one-time PROM or EPROM. Table 22-1 lists the differences among the PD78P064, 78P064Y and the mask ROM versions. Table 22-1. Differences among PD78P064, 78P064Y and Mask ROM Versions Item IC pin VPP pin On-chip mask option split resistors for LCD driving power supply PD78P064, 78P064Y Mask ROM versions None Available None Available None Available User's Manual U10105EJ4V1UM00 439 CHAPTER 22 PD78P064, 78P064Y 22.1 Memory Size Switching Register The PD78P064, 78P064Y allows users to define its internal ROM and high-speed RAM sizes using the memory size switching register (IMS), so that the same memory mapping as that of a mask ROM version with a differentsize internal ROM and high-speed RAM is possible. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to C8H. Figure 22-1. Memory Size Switching Register Format After Reset C8H Symbol 7 6 5 4 0 3 2 1 0 Address FFF0H R/W R/W IMS RAM2 RAM1 RAM0 ROM3 ROM2 ROM1 ROM0 ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity selection 0 0 1 1 1 0 0 1 0 0 0 0 16 Kbytes 24 Kbytes 32 Kbytes Setting prohibited Other than above RAM2 RAM1 RAM0 Internal High-Speed RAM Capacity Selection 0 1 1 1 0 0 512 bytes 1024 bytes Setting prohibited Other than above The IMS settings to give the same memory map as mask ROM versions are shown in Table 22-2. Table 22-2. Examples of Memory Size Switching Register Settings Relevant Mask ROM Version IMS Setting 44H C6H C8H PD78062, 78062Y PD78063, 78063Y PD78064, 78064Y 440 User's Manual U10105EJ4V1UM00 CHAPTER 22 PD78P064, 78P064Y 22.2 PROM Programming The PD78P064 and 78P064Y each incorporate a 32-Kbyte PROM as program memory. To write a program into the PD78P054 or 78P058 PROM, make the device enter the PROM programming mode by setting the levels of the VPP and RESET pins as specified. For the connection of unused pins, see paragraph (2) "PROM Programming Mode" in section 1.4. Caution Write the program in the range of addresses 0000H to 7FFFH (specify the last address as 7FFFH.) The program cannot be correctly written by a PROM programmer which does not have a write address specification function. 22.2.1 Operating modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PD78P064 and PD78P064Y are set to the PROM programming mode. This is one of the operating modes shown in Table 22-3 below according to the setting of the CE, OE, and PGM pins. The PROM contents can be read by setting the read mode. Table 22-3. PROM Programming Operating Modes Pin Operating mode Page data latch Page write Byte write Program verify Program inhibit RESET L VPP +12.5 V VDD +6.5 V CE H H L L x x Read Output disabled Standby x: L or H (1) Read mode Read mode is set by setting CE to L and OE to L. (2) Output disable mode If OE is set to H, data output becomes high impedance and the output disable mode is set. Therefore, if multiple PD78P064s or 78P064Ys are connected to the data bus, data can be read from any one device by controlling the OE pin. +5 V +5V L L H OE L H H L H L L H x PGM H L L H H L H x x Data output High impedance High impedance D0-D7 Data input High impedance Data input Data output High impedance User's Manual U10105EJ4V1UM00 441 CHAPTER 22 PD78P064, 78P064Y (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit. (5) Page write mode After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE=H and OE=H. After this, program verification can be performed by setting CE to L and OE to L. If programming is not performed by one program pulse, repeated write and verify operations are executed X times (X 10). (6) Byte write mode A byte write is executed by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE=L and OE=H. After this, program verification can be performed by setting OE to L. If programming is not performed by one program pulse, repeated write and verify operations are executed X times (X 10). (7) Program verify mode Setting CE to L, PGM to H, and OE to L sets the program verify mode. After writing is performed, this mode should be used to check whether the data was written correctly. (8) Program inhibit mode The program inhibit mode is used when the OE pins, VPP pins and pins D0 to D7 of multiple PD78P064s or 78P064Ys are connected in parallel and any one of these devices must be written to. The page write mode or byte write mode described above is used to perform a write. At this time, the write is not performed on the device which has the PGM pin driven high. 442 User's Manual U10105EJ4V1UM00 CHAPTER 22 PD78P064, 78P064Y 22.2.2 PROM write procedure Figure 22-2. Page Program Mode Flowchart Start Address = G VDD = 6.5 V, VPP = 12.5 V Remark: X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch G = Start address N = Last address of program X=X+1 0.1-ms program pulse No X = 10? Yes Fail Verify 4 Bytes Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass All bytes verified? All Pass Fail End of write Defective product User's Manual U10105EJ4V1UM00 443 CHAPTER 22 PD78P064, 78P064Y Figure 22-3. Page Program Mode Timing Page Program Page Data Latch Program Verify A2-A16 A0, A1 D0-D7 Data Input VPP VPP VDD Data Output VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL 444 User's Manual U10105EJ4V1UM00 CHAPTER 22 PD78P064, 78P064Y Figure 22-4. Byte Program Mode Flowchart Start Remark: Address = G VDD = 6.5 V, VPP = 12.5 V G = Start address N = Last address of program X=0 X=X+1 0.1-ms program pulse No X = 10? Yes Address = Address + 1 Verify Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD Fail Pass All bytes verified? All Pass Fail End of write Defective product User's Manual U10105EJ4V1UM00 445 CHAPTER 22 PD78P064, 78P064Y Figure 22-5. Byte Program Mode Timing Program Program Verify A0-A16 D0-D7 Data Input Data Output VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. Be sure to apply VDD before applying VPP, and remove it after removing VPP. 2. VPP must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied to the VPP pin may have an adverse affect on device reliability. 446 User's Manual U10105EJ4V1UM00 CHAPTER 22 PD78P064, 78P064Y 22.2.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in paragraph, (2) "PROM Programming Mode" in section 1.4. (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of data to be read to pins A0 through A16. (4) Read mode is entered. (5) Data is output to pins D0 through D7. The timing for steps (2) through (5) above is shown in Figure 22-6. Figure 22-6. PROM Read Timing A0-A16 Address Input CE (Input) OE (Input) Hi-Z D0-D7 Data Output Hi-Z User's Manual U10105EJ4V1UM00 447 CHAPTER 22 PD78P064, 78P064Y 22.3 Erasure Procedure (PD78P064KL-T and 78P064YKL-T Only) With the PD78P064KL-T or 78P064YKL-T, it is possible to erase ( or set all contents to FFH) the data contents written in the program memory, and rewrite the memory. The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter. Typically, data is erased by 254-nm ultraviolet light rays. The minimum lighting level to completely erase the written data is shown below. * UV intensity x exposure time: 15 W.s/cm2 or more * Exposure time: 15 to 20 minutes (using a 12 mW/cm2 ultraviolet lamp. A longer exposure time may be required in case of deterioration of the ultraviolet lamp or dirt on the package window). When erasing written data, remove any filter on the window and place the device within 2.5 cm of the lamp tube. 22.4 Opaque Film Masking the Window (PD78P064KL-T and 78P064YKL-T Only) To prevent unintentional erasure of the EPROM contents by light and to prevent internal circuits from mulfunction due to light coming in through the erasure window, mask the window with opaque film after writing the EPROM. 22.5 Screening of One-Time PROM Versions One-time PROM versions ( PD78P064GC-7EA, PD78P064YGC-7EA, PD78P064GF-3BA, and PD78P064YGF-3BA) cannot be fully tested by NEC before shipment due to the structure of one-time PROM. Therefore, after users have written data into the PROM, screening should be implemented by user: that is, store devices at high temperature for one day as specified below, and verify their contents after the devices have returned to room temperature. Storage Temperature 125C Storage Time 24 hours * For users who do not wish to implement screening by themselves, NEC provides such users with a charged service in which NEC performs a series of processes from writing one-time PROMs and screening them to verifying their contents for users by request. The PROM version devices which provide this service are called QTOPTM microcontrollers. For details, please consult an NEC sales representative. 448 User's Manual U10105EJ4V1UM00 CHAPTER 23 INSTRUCTION SET This chapter describes each instruction set of the PD78064 and 78064Y subseries as list table. For details of its operation and operation code, refer to the separate document "78K/0 series USER'S MANUAL--Instruction (U12326E)." User's Manual U10105EJ4V1UM00 449 CHAPTER 23 INSTRUCTION SET 23.1 Legends Used in Operation List 23.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. Each symbol has the following meaning. * # : Immediate data specification * ! : Absolute address specification * $ : Relative address specification * [ ] : Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $, and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 23-1. Operand Identifiers and Description Methods Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Note Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7), AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbolNote Special-function register symbol (16-bit manipulatable register even addresses only)Note FE20H-FF1FH Immediate data or labels FE20H-FF1FH Immediate data or labels (even address only) 0000H-FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H-0FFFH Immediate data or labels 0040H-007FH Immediate data or labels (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3 Addresses from FFD0H to FFDFH cannot be accessed with these operands. For special-function register symbols, refer to Table 5-4 Special-Function Register List. Remark 450 User's Manual U10105EJ4V1UM00 CHAPTER 23 INSTRUCTION SET 23.1.2 Description of "operation" column A X B C D E H L AX BC DE HL PC SP PSW CY AC Z RBS IE () : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter : Stack pointer : Program status word : Carry flag : Auxiliary carry flag : Zero flag : Register bank select flag : Interrupt request enable flag : Memory contents indicated by address or register contents in parentheses : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) ---- : Inverted data addr16 : 16-bit immediate data or label jdisp8 : Signed 8-bit data (displacement value) 23.1.3 Description of "flag operation" column (Blank) : Nt affected 0 1 x R : Cleared to 0 : Set to 1 : Set/cleared according to the result : Previously saved value is restored NMIS : Non-maskable interrupt servicing flag xH, xL : Higher 8 bits and lower 8 bits of 16-bit register User's Manual U10105EJ4V1UM00 451 CHAPTER 23 INSTRUCTION SET 23.2 Operation List Instruction Mnemonic Group Clock Operands r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A MOV 8-bit data transfer A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A A, r A, saddr A, sfr A, !addr16 XCH A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Note 3 Note 3 Flag Operation r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A (HL + B) (HL + B) A A (HL + C) (HL + C) A Ar A (saddr) A (sfr) A (addr16) A (DE) A (HL) A (HL + byte) A (HL + B) A (HL + C) x x x x x x Z AC CY Byte 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 1 2 2 3 1 1 2 2 2 Note 1 Note 2 4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8 - 7 7 - - 5 5 5 5 9 9 7 5 5 5 5 5 5 9 9 7 7 7 7 - 6 6 10 6 6 10 10 10 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 452 User's Manual U10105EJ4V1UM00 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX Byte 3 4 4 2 2 2 2 Note 3 Note 3 Note 1 Note 2 Flag Operation Z AC CY rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX AX (addr16) (addr16) AX AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 10 10 8 8 8 8 - - 12 12 - - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 16-bit data MOVW transfer AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX 1 1 3 3 XCHW AX, rp A, #byte saddr, #byte A, r r, A Note 3 1 2 3 Note 4 2 2 2 3 1 2 2 2 2 3 ADD A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] 8-bit operation A, [HL + C] A, #byte saddr, #byte A, r r, A A, saddr ADDC A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 4 2 2 2 3 1 2 2 2 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Only when rp = BC, DE or HL 4. Except "r = A" Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. User's Manual U10105EJ4V1UM00 453 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands A, #byte saddr, #byte A, r r, A A, saddr Note 3 Flag Operation Z AC CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY AA AA rr AA AA AA AA AA AA byte byte (saddr) (saddr) r A (saddr) (addr16) (HL) (HL + byte) (HL + B) (HL + C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Byte 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 Note 1 Note 2 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 SUB A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A 2 2 2 3 1 2 2 2 2 3 8-bit operation SUBC A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A Note 3 2 2 2 3 1 2 2 2 AND A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 454 User's Manual U10105EJ4V1UM00 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands A, #byte saddr, #byte A, r r, A A, saddr Note 3 Flag Operation Z AC CY A A byte (saddr) (saddr) byte AA r rr A A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) AA AA rr AA AA AA AA AA AA A - byte (saddr) - byte A-r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C) A (saddr) (addr16) (HL) (HL + byte) (HL + B) (HL + C) byte byte (saddr) (saddr) r x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Byte 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 Note 1 Note 2 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 OR A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A 2 2 2 3 1 2 2 2 2 3 8-bit operation XOR A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A Note 3 2 2 2 3 1 2 2 2 CMP A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. User's Manual U10105EJ4V1UM00 455 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group ADDW 16-bit operation Multiply/ divide SUBW CMPW MULU DIVUW INC Increment/ DEC decrement INCW DECW ROR ROL RORC Rotate ROLC ROR4 ROL4 ADJBA ADJBS Clock Operands AX, #word AX, #word AX, #word X C r saddr r saddr rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL] Byte 3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2 2 2 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit 3 3 2 3 2 3 3 2 3 2 Note 1 Note 2 Flag Operation Z AC CY AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 6 6 6 16 25 2 4 2 4 4 4 2 2 2 2 10 10 4 4 6 - 4 - 6 6 - 4 - 6 - - - - - - 6 - 6 - - - - - - 12 12 - - 7 7 - 7 7 8 8 - 8 8 BCD adjust Bit manipulate CY, [HL].bit MOV1 saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 456 User's Manual U10105EJ4V1UM00 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands CY, saddr.bit CY, sfr.bit Byte 3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1 Note 1 Note 2 Flag Operation Z AC CY CY CY CY CY CY CY CY CY CY CY (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit x x x x x x x x x x x x x x x 6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2 7 7 - 7 7 7 7 - 7 7 7 7 - 7 7 6 8 - 6 8 6 8 - 6 8 - - - AND1 CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY CY CY CY CY CY CY CY CY sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY x x x x (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit OR1 CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit Bit manipulate XOR1 CY, A.bit CY, PSW. bit CY, [HL].bit saddr.bit sfr.bit (saddr.bit) 1 SET1 A.bit PSW.bit [HL].bit saddr.bit sfr.bit x CLR1 A.bit PSW.bit [HL].bit x SET1 CLR1 NOT1 CY CY CY 1 0 x Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. User's Manual U10105EJ4V1UM00 457 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group CALL Clock Operands Byte Note 1 Note 2 Flag Operation Z AC CY (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 R R R R R R !addr16 3 7 - CALLF !addr11 2 5 - CALLT Call/return BRK [addr5] 1 6 - 1 6 - RET 1 6 - RETI 1 6 - RETB PSW PUSH rp Stack manipulate PSW POP rp SP, #word MOVW SP, AX AX, SP Unconditional branch !addr16 BR $addr16 AX BC Conditional BNC branch BZ BNZ $addr16 $addr16 $addr16 $addr16 1 1 1 1 1 4 2 2 3 2 2 2 2 2 2 6 2 4 2 4 - - - 6 6 8 6 6 6 6 - - - - - 10 8 8 - - - - - - - R R R Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 458 User's Manual U10105EJ4V1UM00 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands saddr.bit, $addr16 sfr.bit, $addr16 Byte 3 4 3 3 3 4 4 3 4 3 4 Note 1 Note 2 Flag Operation Z AC CY PC PC + 3 + jdisp8 if(saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if(saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if(saddr) 0 RBS1, 0 n No Operation IE 1(Enable Interrupt) IE 0(Disable Interrupt) Set HALT Mode Set STOP Mode x x x 8 - 8 - 10 10 - 8 - 10 10 9 11 - 9 11 11 11 - 11 11 12 BT A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 BF A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 Conditional branch saddr.bit, $addr16 sfr.bit, $addr16 BTCLR A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 B, $addr16 DBNZ C, $addr16 saddr. $addr16 SEL NOP CPU control EI DI HALT STOP RBn 4 3 4 3 2 2 3 2 1 2 2 2 2 - 8 - 10 6 6 8 4 2 - - 6 6 12 - 12 12 - - 10 - - 6 6 - - Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. User's Manual U10105EJ4V1UM00 459 CHAPTER 23 INSTRUCTION SET 23.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ 460 User's Manual U10105EJ4V1UM00 CHAPTER 23 INSTRUCTION SET Second Operand #byte First Operand A ADD ADDC SUB SUBC AND OR XOR CMP XCH ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP r1 sfr saddr MOV MOV MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV XCH XCH ADD XCH ADD XCH XCH ADD A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] [HL + B] $addr16 [HL + C] 1 ROR ROL RORC ROLC None MOV MOV MOV MOV MOV MOV MOV MOV XCH ADD ADDC ADDC SUB SUB SUBC SUBC AND AND OR XOR CMP OR XOR CMP ADDC ADDC SUB SUB SUBC SUBC AND AND OR XOR CMP OR XOR CMP INC DEC DBNZ DBNZ INC DEC PUSH POP [DE] [HL] MOV MOV ROR4 ROL4 [HL + byte] [HL + B] [HL + C] X C Note Except r = A MOV MULU DIVUW User's Manual U10105EJ4V1UM00 461 CHAPTER 23 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word 1st Operand AX ADDW SUBW CMPW rp MOVW MOVWNote INCW DECW PUSH POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW AX rpNote sfrp saddrp !addr16 SP None Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit First Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None 462 User's Manual U10105EJ4V1UM00 CHAPTER 23 INSTRUCTION SET (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP !addr16 !addr11 [addr5] $addr16 User's Manual U10105EJ4V1UM00 463 [MEMO] 464 User's Manual U10105EJ4V1UM00 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the PD78064 and 78P064Y subseries. Figure A-1 shows the configuration example of the tools. Figure A-1. Development Tool Configuration * Real-time OS (RX78K/0) OS (MX78K0) Fuzzy Inference Development Support System PG-1500 Controller Assembler Package (RA78K/0) Device File (DF78064) C Compiler Package (CC78K/0) System Simulator (SM78K0) Screen Debugger (SD78K/0) C Library Source File (CC78K/0-L) Cetronics I/F PROM Progammer PG-1500 Programmer Adapter PA-78P064GC PA-78P064GF PA-78P064KL-T RS-232-C RS-232-C Host Machine PC-9800 Series IBM PC/AT and their compatibles EWS (See Note1) In-Circuit Emulator IE-78000-R Emulation Board IE-78064-R-EM PROM Version Emulation Probe EP-78064GC-R EP-78064GF-R PD78P064 PD78P064Y Note2 Note2 Note3 User System Notes 1. Except system simulator, screen debugger, fuzzy inference development support system, and PG1500 controller. 2. EV-9200GF-100 (when EP-78064GF-R or 100-pin ceramic WQFN version is used) 3. EV-9500GC-100 (EP-78064GC-R is used) Remark Though in this diagram, 3.5-inch floppy disks are shown as software delivery media. Other media are also available. User's Manual U10105EJ4V1UM00 465 APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software This assembler converts a program written in mnemonics into an object code executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This data file is used together with DF78064 device file (option). Part Number: SxxxxRA78K0 RA78K/0 (Assembler Package) CC78K/0 (C Compiler Package) This compiler converts a program written in C language into an object code executable with a microcontroller. This data file is used together with RA78K/0 assembler package and DF78064 device file (option). Part Number: SxxxxCC78K0 DF78064 (Device File) (See Note) Device file for the PD78064 and 78064Y subseries. This data file is used together with RA78K/0, CC78K/0, SM78K0, and SD78K/0. Part Number: SxxxxDF78064 CC78K/0-L (C Compiler Library Source File) Source program of a function configurating object library included in CC78K/0 C compiler. This file is necessary when customers change the object library in CC78K/0 following their specifications. Part Number: SxxxxCC78K0-L Note This device file can be used for any of RA78K/0, CC78K/0, SM78K0, and SD78K/0. xxxx of the part number differs depending on the host machine and OS used. Refer to the table below. Sxxxx RA78K0 Sxxxx CC78K0 Sxxxx DF78064 Sxxxx CC78K0-L xxxx 5A13 5A10 7B13 7B10 3H15 IBM PC/AT or compatible machine HP9000 series 300TM HP9000 series 700TM HP-UXTM (rel.7.05B) HP-UX (rel.9.01) SunOSTM Host Machine PC-9800 series OS MS-DOS (ver. 3.30 - 5.00A)Note Refer to Section A.4. Medium 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HC 5-inch 2HC Cartidge tape (QIC-24) Digital audio tape (DAT) 3K15 3M15 SPARCstationTM EWS-4800 series (RISC) (rel.4.1.1) Cartidge tape (QIC-24) Remark * 3P16 EWS-UX/V (rel.4.0) Note The task swap function is not available with this software though the function is provided in MS-DOS version 5.0 or later. 466 User's Manual U10105EJ4V1UM00 APPENDIX A DEVELOPMENT TOOLS A.2 PROM Programming Tools Hardware PG-1500 This is a PROM programmer capable of programming the single-chip microcontroller incorporating PROM by manipulating from the standalone or host machine through connection of an optional PROM programmer adapter and attached board. It can also program representative PROMs ranging from 256K bits to 4M bits. PA-78P064GC PA-78P064GF PA-78P064KL-T PROM programmer adapter for the PD78P064 and 78P064Y. Used connected to the PG-1500. PA-78P064GC : 100-pin plastic QFP (14 x 14 mm) PA-78P064GF : 100-pin plastic QFP (14 x 20 mm) PA-78P064KL-T : 100-pin ceramic WQFN (14 x 20 mm) Software PG-1500 Controller The PG-1500 is controlled in the host machine through connection with the host machine and PG-1500 via serial and parallel interfaces. Host Machine OS Medium Part Number (Product Name) PC-9800 series MS-DOS Ver.3.30 to Ver.5.00ANote IBM PC/AT or compatibles Note Refer to Section A.4. 3.5-inch 2HC 5-inch 2HC 3.5-inch 2HD 5-inch 2HD S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500 The task swap function is not available with this software though the function is provided in MS-DOS version 5.0 or later. User's Manual U10105EJ4V1UM00 467 APPENDIX A DEVELOPMENT TOOLS A.3 A.3.1 Debugging Tool Hardware This in-circuit emulator helps users in debugging hardware and software of an application system that includes a 78K/0 series device. Use this incircuit emulator in combination with an emulation probe. Connect with the host machine and the PROM programmer for efficient debugging. IE-78000-R (In-circuit emulator) IE-78064-R-EM (Emulation board) This board is for the PD78064, 78064Y subseries, and supports voltages from 3 to 5.5 V. EP-78064GC-R (Emulation probe) This probe is designed for 100-pin plastic QFP (14 x 14 mm) and can also be used for other devices such as the PD78064, 78064Y subseries. This probe set includes a 100-pin conversion adapter EV-9500GC-100 for easier development of user systems. TGC-100SDW (Conversion adapter) This adapter connects the EP-78064GC-R to the user system board designed for 100-pin plastic QFP (14 x 14 mm). EP-78064GF-R (Emulation probe) This probe is designed for 100-pin plastic QFP (14 x 20 mm) and can also be used for other devices such as the PD78064, 78064Y subseries. This probe set includes a 100-pin conversion socket EV-9200GF-100 for easier development of user systems. EV-9200GF-100 (Conversion socket) This socket connects the EP-78064GF-R to the user system board designed for a 100-pin plastic QFP (14 x 20 mm). EV-9900 (Device remover) This is a jig used to remove the PD78P064KL-T and 78P064YKL-T from the EV-9200GF-100. Remark The EV-9500GC-100 is sold in units of one. The EV-9200GF-100 comes in a set of five and is sold in one-unit sets. 468 User's Manual U10105EJ4V1UM00 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software This simulator simulates operations of the target system from a Windows TM-installed host computer, enabling debuggung in C source level or assembler level. By using SM78K0, logical and performance verification processes can be performed independently of hardware development work without using IE-78000-R in-circuit emulator, which leads to reduction in development workload and improvement in software quality. This system simulator is used together with the DF78064 device file (option). Part Number: SxxxxSM78K0 SM78K0 (System simulator) * SD78K/0 (Screen debugger) This debugger is a program which controls the IE-78000-R in-circuit emulator from the host computer. The in-circuit emulator must be connected to the host computer via a serial interface (RS-232-C) cable. This debugger is used together with the DF78064 device file (option). Part Number: SxxxxSD78K0 DF78064 (Device File) (See Note) Device file for the PD78064 and 78064Y subseries. This device file is used together with the SM78K0, CC78K/0, RA78K0, and SD78K/0 (option). Part Number: SxxxxDF78064 Note This device file can be used for any of RA78K/0, CC78K/0, SM78K0, and SD78K/0. xxxx of the part number differs depending on the host machine and OS used. Refer to the table below. Sxxxx SM78K0 xxxx AA13 AA10 AB13 AB10 BB13 BB10 IBM PC/AT or compatible machine (on Japanese Windows) IBM PC/AT or compatible machine (on English Wondows) Sxxxx SD78K0 Sxxxx DF78064 xxxx 5A13 5A10 7B13 7B10 Note IBM PC/AT or compatible machine Host Machine PC-9800 series OS MS-DOS (ver. 3.30 - 5.00A)Note Refer to Section A.4. Medium 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HC 5-inch 2HC Refer to Section A.4. Host Machine PC-9800 series OS MS-DOS (ver. 3.30 - 5.00A)Note + Windows (ver. 3.0 and 3.1) Refer to Section A.4. Medium 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HC 5-inch 2HC 3.5-inch 2HC 5-inch 2HC Remark The task swap function is not available with this software though the function is provided in MS-DOS version 5.0 or later. User's Manual U10105EJ4V1UM00 469 APPENDIX A DEVELOPMENT TOOLS * A.4 Operating Systems for IBM PC The following operating systems are available for IBM PC. If SM78K0 and FE9200 (see Section B.2 "Fuzzy Inference Development Support System") are to be operated, Windows version 3.0 or 3.1 is also required. OS PC DOS Version Version 3.3 through 6.3 J6.1/V through J6.3/V (see Note) IBM DOSTM MS-DOS J5.02/V (see Note) Version 5.0 through 6.2 5.0/V through 6.2V (see Note) Note Supports English versions only. Caution The task swap function is not available with this software though the function is provided in MS-DOS version 5.0 or later. 470 User's Manual U10105EJ4V1UM00 APPENDIX A DEVELOPMENT TOOLS System-up method from other in-circuit emulator to IE-78000-R When you already have an in-circuit emulator for the 78K series or the 75X series, you can use that in-circuit emulator as the equivalent of a 78K/0 in-circuit emulator IE-78000-R by replacing the internal break board with the IE-78000-R-BK. Series Name 75X Series 78K/I Series 78K/II Series In-circuit Emulator Owned IE-75000-R*, IE-75001-R IE-78130-R, IE-78140-R IE-78230-R*, IE-78230-R-A IE-78240-R*, IE-78240-R-A 78K/III Series IE-78320-R*, IE-78327-R IE-78330-R, IE-78350-R Remark * : Available for maintenance purpose only. Board to be Purchased IE-78000-R-BK User's Manual U10105EJ4V1UM00 471 APPENDIX A DEVELOPMENT TOOLS Drawing for Conversion Adapter (TGC-100SDW) Figure A-2. TGC-100SDW Drawing (For Reference Only) (Unit: mm) X C A B N L M T O X FED HIJK Protrusion height V W PQRS U G Y e a n m g I j i f h ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 21.55 0.5x24=12 0.5 0.5x24=12 15.0 21.55 INCHES 0.848 0.020x0.945=0.472 0.020 0.020x0.945=0.472 0.591 0.848 ITEM a b c d e f g h i j k l m n MILLIMETERS 14.45 1.850.25 3.5 2.0 3.9 0.25 INCHES 0.569 0.0730.010 0.138 0.079 0.154 0.010 Z k d c b 3.55 10.9 13.3 15.7 18.1 13.75 0.5x24=12.0 1.1250.3 1.1250.2 7.5 10.0 11.3 18.1 0.140 0.429 0.524 0.618 0.713 0.541 0.020x0.945=0.472 0.0440.012 0.0440.008 0.295 0.394 0.445 0.713 4.5 16.0 1.1250.3 0~5 5.9 0.8 2.4 2.7 0.177 0.630 0.0440.012 0.000~0.197 0.232 0.031 0.094 0.106 TGC-100SDW-G1E 5.0 5.0 4- 1.3 1.8 C 2.0 0.197 0.197 4- 0.051 0.071 C 0.079 0.9 0.3 0.035 0.012 note: Product by TOKYO ELETECH CORPORATION. 472 User's Manual U10105EJ4V1UM00 APPENDIX A DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200GF-100) Figure A-3. EV-9200GF-100 Drawing (For Reference Only) Based on EV-9200GF-100 (1) Package drawing (in mm) A B F M N E O R D C S K EV-9200GF-100 1 No.1 pin index P G H I EV-9200GF-100-G0E ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 24.6 21 15 18.6 4-C 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 INCHES 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.76 0.323 0.315 0.098 0.079 0.014 2.3 1.5 0.091 0.059 Q L J User's Manual U10105EJ4V1UM00 473 APPENDIX A DEVELOPMENT TOOLS Figure A-4. EV-9200GF-100 Footprint (For Reference Only) Based on EV-9200GF-100 (2) Pad drawing (in mm) G J K D H F E L I C B A EV-9200GF-100-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 26.3 21.6 INCHES 1.035 0.85 0.650.02 x 29=18.850.05 0.026+0.001 x 1.142=0.742+0.002 -0.002 -0.002 0.650.02 x 19=12.350.05 0.026+0.001 x 0.748=0.486+0.003 -0.002 -0.002 15.6 20.3 12 0.05 6 0.05 0.35 0.02 0.614 0.799 0.472+0.003 -0.002 0.236+0.003 -0.002 0.014+0.001 -0.001 2.36 0.03 2.3 1.57 0.03 0.093+0.001 -0.002 0.091 0.062+0.001 -0.002 Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). 474 User's Manual U10105EJ4V1UM00 APPENDIX B EMBEDDED SOFTWARE This section describes the embedded software which are provided for the PD78064 and 78064Y subseries to allow users to develop and maintain the application program for these subseries. B.1 Real-time OS (1/2) RX78K/0 is a real-time OS which is based on the ITRON specification. Supplied with the RX78K/0 nucleus and a tool to prepare multiple information tables (configurator). When using the RX78K/0, the RA78K/0 assembler package (option) is necessary. Part Number: SxxxxRX78013- RX78K/0 Real-Time OS Caution When purchasing the RX78K/0, fill in the purchase application form in advance, and sign the Use Approval Contract. Remark xxxx and of the part number differs depending on the host machine and OS used. Refer to the table below. SxxxxRX78013- 001 100K 001M 010M S01 xxxx 5A13 5A10 7B13 7B10 3H15 3P16 3K15 3M15 Note IBM PC/AT or compatible machine HP9000 series 300 HP9000 series 700 SPARCstation EWS-4800 series (RISC) HP-UX (rel.7.05B) HP-UX (rel.9.01) SunOS (rel.4.1.1) EWS-UX/V (rel.4.0) Source program Host Machine PC-9800 series Product outline Evaluation object Mass-production object Max. No. for use in mass production Do not use for mass production 100,000 1,000,000 10,000,000 Source program for mass-production object OS MS-DOS Medium 3.5-inch 2HD (ver. 3.30 - 5.00A)Note 5-inch 2HD Refer to Section A.4. 3.5-inch 2HC 5-inch 2HC Cartridge tape (QIC-24) Digital tape (DAT) Cartridge tape (QIC-24) * The task swap function is not available with this software though the function is provided in MS-DOS version 5.0 or later. User's Manual U10105EJ4V1UM00 475 APPENDIX B EMBEDDED SOFTWARE * B.1 Real-time OS (2/2) MX78K0 OS MX78K/0 is an OS for subsets based on the ITRON specification. Supplied with the MX78K0 nucleus. This OS manages tasks, events, and time. In task management operation, it controls the execution orders of tasks, and switches processing to the task to be executed next. Part Number: SxxxxMX78K0- xxxx and of the part number differs depending on the host machine and OS used. Refer to the table below. SxxxxMX78K0- 001 xx S01 Product outline Evaluation object Mass-production object Source program Remark Use for preproduction. Use for mass-production. Available only when purchasing massproduction object xxxx 5A13 5A10 7B13 7B10 3H15 3P16 3K15 3M15 Note IBM PC/AT or compatible machine HP9000 series 300 HP9000 series 700 SPARCstation EWS-4800 series (RISC) HP-UX (rel.7.05B) HP-UX (rel.9.01) SunOS (rel.4.1.1) EWS-UX/V (rel.4.0) Host Machine PC-9800 series OS MS-DOS Medium 3.5-inch 2HD Remark (ver. 3.30 - 5.00A)Note 5-inch 2HD Refer to Section A.4. 3.5-inch 2HC 5-inch 2HC Cartridge tape (QIC-24) Digital tape (DAT) Cartridge tape (QIC-24) The task swap function is not available with this software though the function is provided in MS-DOS version 5.0 or later. 476 User's Manual U10105EJ4V1UM00 APPENDIX B EMBEDDED SOFTWARE B.2 Fuzzy Inference Development Support System FE9000/FE9200 (Fuzzy Knowledge Data Creation tool) Program supporting input of fuzzy knowledge data (fuzzy rule and membership function), editing (edit), and evaluation (simulation). FE9200 operates on Windows. Part number: SxxxxFE9000 (PC-9800 series) SxxxxFE9200 (IBM PC/AT or compatible machine) FT9080/FT9085 (Translator) Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to RA78K/0 assembler source program. Part number: SxxxxFT9080 (PC-9800 series) SxxxxFT9085 (IBM PC/AT or compatible machine) FI78K0 (Fuzzy Inference Module) Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge data converted by translator. Part number: SxxxxFI78K0 (PC-9800 series, IBM PC/AT or compatible machine) FD78K0 (Fuzzy Inference Debugger) Support software evaluating and adjusting fuzzy knowledge data at hardware level by using in-circuit emulator. Part number: Remark SxxxxFD78K0 (PC-9800 series, IBM PC/AT or compatible machine) xxxx of the part number differs depending on the host machine and OS used. Refer to the table below. SxxxxFE9000 SxxxxFT9080 SxxxxFI78K0 SxxxxFD78K0 xxxx 5A13 5A10 Host Machine PC-9800 series OS MS-DOS Medium 3.5-inch 2HD (ver. 3.30 - 5.00A)Note 5-inch 2HD SxxxxFE9200 SxxxxFT9085 SxxxxFI78K0 SxxxxFD78K0 xxxx 7B13 7B10 Host Machine IBM PC/AT or compatible machine OS Refer to Section A.4. Medium 3.5-inch 2HC 5-inch 2HC Note The task swap function is not available with this software though the function is provided in MS-DOS version 5.0 or later. User's Manual U10105EJ4V1UM00 477 [MEMO] 478 User's Manual U10105EJ4V1UM00 APPENDIX C REGISTER INDEX C.1 [A] A/D converter input select register (ADIS) ... 224 A/D converter mode register (ADM) ... 222 A/D conversion result register (ADCR) ... 221 Asynchronous serial interface status register (ASIS) ... 345, 354 Asynchronous serial interface mode register (ASIM) ... 343, 351, 353, 366 Register Name Index [B] Baud rate generator control register (BRGC) ... 346, 355, 367 [C] Capture/compare control register 0 (CRC0) ... 139 Capture/compare register 00 (CR00) ... 134 Capture/compare register 01 (CR01) ... 134 Clock timer mode control register (TMC2) ... 199 Compare register 10 (CR10) ... 177 Compare register 20 (CR20) ... 177 [E] 8-bit timer mode control register (TMC1) ... 180 8-bit timer output control register (TOC1) ... 181 8-bit timer register 1 (TM1) ... 8-bit timer register 2 (TM2) ... 177 177 External interrupt mode register 0 (INTM0) ... 142, 409 External interrupt mode register 1 (INTM1) ... 225, 409 [I] Interrupt mask flag register 0H (MK0H) ... 407 Interrupt mask flag register 0L (MK0L) ... 407 Interrupt mask flag register 1L (MK1L) ... 407, 424 Interrupt request flag register 0H (IF0H) ... 406 Interrupt request flag register 0L (IF0L) ... 406 Interrupt request flag register 1L (IF1L) ... 406, 424 Interrupt timing specification register (SINT) ... 248, 266, 284, 301, 311, 321 [K] Key return mode register (KRM) ... 109, 425 User's Manual U10105EJ4V1UM00 479 APPENDIX C REGISTER INDEX [L] LCD display control register (LCDC) ... 376 LCD display mode register (LCDM) ... 374 [M] Memory size switching register (IMS) ... 440 [O] Oscillation mode select register (OSMS) ... 117 Oscillation stabilization time select register (OSTS) ... 428 [P] Port 0 (P0) ... Port 1 (P1) ... 92 94 Port 2 (P2) ... 95, 97 Port 3 (P3) ... 99 Port 7 (P7) ... 100 Port 8 (P8) ... 102 Port 9 (P9) ... 103 Port 10 (P10) ... 104 Port 11 (P11) ... 105 Port mode register 0 (PM0) ... 106 Port mode register 1 (PM1) ... 106 Port mode register 2 (PM2) ... 106 Port mode register 3 (PM3) ... 106, 141, 182, 213, 218 Port mode register 7 (PM7) ... 106 Port mode register 8 (PM8) ... 106 Port mode register 9 (PM9) ... 106 Port mode register 10 (PM10) ... 106 Port mode register 11 (PM11) ... 106 Priority specification flag register 0H (PR0H) ... 408 Priority specification flag register 0L (PR0L) ... 408 Priority specification flag register 1L (PR1L) ... 408 Processor clock control register (PCC) ... 115 Pull-up resistor option register H (PUOH) ... 109 Pull-up resistor option register L (PUOL) ... 109 [R] Receive buffer register (RXB) ... 341 Receive shift register (RXS) ... 341 480 User's Manual U10105EJ4V1UM00 APPENDIX C REGISTER INDEX [S] Sampling clock select register (SCS) ... 143, 411 Serial bus interface control register (SBIC) ... 246, 252, 264, 283, 299, 305, 310, 320 Serial I/O shift register 0 (SIO0) ... 240, 294 Serial operating mode register 0 (CSIM0) ... 244, 250, 263, 282, 298, 304, 309, 319 Serial operating mode register 2 (CSIM2) ... 342, 350, 352, 365 16-bit timer mode control register (TMC0) ... 137 16-bit timer output control register (TOC0) ... 140, 147, 149 16-bit timer register (TM0) ... 134 Slave address register (SVA) ... 240, 286, 294 Successive approximation register (SAR) ... 221 [T] Timer clock select register 0 (TCL0) ... 135, 211 Timer clock select register 1 (TCL1) ... 178 Timer clock select register 2 (TCL2) ... 196, 204, 216 Timer clock select register 3 (TCL3) ... 242, 296 Transmit shift register (TXS) ... 341 [W] Watchdog timer mode register (WDTM) ... 206 User's Manual U10105EJ4V1UM00 481 APPENDIX C REGISTER INDEX C.2 [A] Register Symbol Index ADCR: A/D conversion result register ... 221 ... 224 ADIS: A/D converter input select register ADM: A/D converter mode register ... 222 ... 343, 351, 353, 366 ASIM: Asynchronous serial interface mode register ASIS: Asynchronous serial interface status register ... 345, 354 [B] BRGC: Baud rate generator control register ... 346, 355, 367 [C] CR00: Capture/compare register 00 CR01: Capture/compare register 01 CR10: Compare register 10 CR20: Compare register 20 ... 177 ... 177 ... 139 ... 244, 250, 263, 282, 298, 304, 309, 319 ... 342, 350, 352, 365 ... 134 ... 134 CRC0: Capture/compare control register 0 CSIM0: Serial operating mode register 0 CSIM2: Serial operating mode register 2 [I] IF0H: Interrupt request flag register 0H IF0L: Interrupt request flag register 0L IF1L: Interrupt request flag register 1L IMS: Memory size switching register ... 406 ... 406 ... 406, 424 ... 440 ... 142, 409 ... 225, 409 INTM0: External interrupt mode register 0 INTM1: External interrupt mode register 1 [K] KRM: Key return mode register ... 109, 425 [L] LCDC: LCD display control register LCDM: LCD display mode register ... 376 ... 374 [M] MK0H: Interrupt mask flag register 0H ... 407 MK0L: Interrupt mask flag register 0L ... 407 MK1L: Interrupt mask flag register 1L ... 407, 424 482 User's Manual U10105EJ4V1UM00 APPENDIX C REGISTER INDEX [O] OSMS: Oscillation mode select register ... 117 ... 428 OSTS: Oscillation stabilization time select register [P] P0: Port 0 P1: Port 1 P2: Port 2 P3: Port 3 P7: Port 7 P8: Port 8 P9: Port 9 ... 92 ... 94 ... 95, 97 ... 99 ... 100 ... 102 ... 103 ... 104 ... 105 ... 115 P10: Port 10 P11: Port 11 PCC: Processor clock control register PM0: Port mode register 0 PM1: Port mode register 1 PM2: Port mode register 2 PM3: Port mode register 3 PM7: Port mode register 7 PM8: Port mode register 8 PM9: Port mode register 9 ... 106 ... 106 ... 106 ... 106, 141, 182, 213, 218 ... 106 ... 106 ... 106 ... 106 ... 106 ... 408 ... 408 ... 408 PM10: Port mode register 10 PM11: Port mode register 11 PR0H: Priority specification flag register 0H PR0L: Priority specification flag register 0L PR1L: Priority specification flag register 1L PUOH: Pull-up resistor option register H PUOL: Pull-up resistor option register L ... 109 ... 109 [R] RXB: Receive buffer register ... 341 RXS: Receive shift register ... 341 [S] SAR: Successive approximation register ... 221 SBIC: Serial bus interface control register SCS: Sampling clock select register ... 246, 252, 264, 283, 299, 305, 310, 320 ... 143, 411 ... 248, 266, 284, 301, 311, 321 SINT: Interrupt timing specification register SIO0: Serial I/O shift register 0 SVA: Slave address register ... 240, 294 ... 240, 286, 294 User's Manual U10105EJ4V1UM00 483 APPENDIX C REGISTER INDEX [T] TCL0: Timer clock select register 0 TCL1: Timer clock select register 1 TCL2: Timer clock select register 2 TCL3: Timer clock select register 3 TM0: 16-bit timer register TM1: 8-bit timer register 1 TM2: 8-bit timer register 2 ... 134 ... 135, 211 ... 178 ... 196, 204, 216 ... 242, 296 ... 177 ... 177 ... 137 ... 180 ... 199 ... 140, 147, 149 ... 181 TMC0: 16-bit timer mode control register TMC1: 8-bit timer mode control register TMC2: Clock timer mode control register TOC0: 16-bit timer output control register TOC1: 8-bit timer output control register TXS: Transmit shift register ... 341 [W] WDTM: Watchdog timer mode register ... 206 484 User's Manual U10105EJ4V1UM00 APPENDIX D REVISION HISTORY The revision history is shown below. The chapters appearing in the revised-chapter column indicate those of the corresponding edition. (1/5) Edition chapter Second Major changes Development of the PD78063 and PD78064 has now been completed. PD78P064KL-T: Being planned -> Being developed Operating supply voltage range: 2.7 to 6.0 V -> 2.0 to 6.0 V Input/output circuit type of pins P10/ANI0 to P17/ANI7: 9-B -> 11 Recommended connection of unused IC pins (masked-ROM product): "Connect to VSS." -> "Connect to V SS directly." Figure 5-2 has been added. The wiring diagram of the oscillator has been modified. Table 6-5 has been modified. A note has been added to timer clock selection register 0 format. A caution has been added to 16-bit timer mode control register format. (6) and (7) have been added to Section 6.5. Tables 8-1 and 8-3 have been modified. A note has been added to timer clock selection register 0 format. A note has been added to A/D converter mode register format. Port mode register 2 (PM2) has been added to Table 13-2. Serial interface channel 0 block diagram has been modified. Serial operating mode register 0 format has been modified. Serial bus interface control register format has been modified. Interrupt timing specification register format has been modified. Figure 13-7 has been modified. Figures 13-20 and 13-21 have been modified. Table 13-3: "<3> Reception of address signal" has been added as the condition for output of the ready signal. (e) has been added to (10) of Section 13.4.3. Figure 13-31 has been modified. Chapter 8 Chapter 10 Chapter 12 Chapter 13 Chapter 6 Chapter 5 Chapter 1 Chapter 2 Revised Throughout User's Manual U10105EJ4V1UM00 485 APPENDIX D REVISION HISTORY (2/5) Edition chapter Second Major changes Revised Serial interface channel 2 block diagram has been modified. Serial operating mode register 2 format has been modified. Asynchronous serial interface mode register format has been modified. Table 14-2 has been modified. (3) has been added to Section 14.4.2. A note has been added to interrupt request flag register format. A note has been added to interrupt mask flag register format. Table 16-3 has been modified. Figures 16-15 and 16-16 have been modified. Table 17-1 has been modified. A remark has been added to Figure 17-2. Table 17-3 has been modified. Language Processing Software, Debugging Tools, and Development Tool Configurations have been modified. System Upgrade Method to an IE-78000-R System from Other In-Circuit Emulators has been added. Drawing and Footprint for Conversion Socket (EV-9200GF-100) has been added. Appendix B has been added. Chapter 14 Chapter 16 Chapter 17 Appendix A Appendix B 486 User's Manual U10105EJ4V1UM00 APPENDIX D REVISION HISTORY (3/5) Edition chapter Third Major changes Development of the PD78062GC, PD78062GF, PD78P064GC, and PD78P064GF has already been completed. Section 1.6 has been changed. Section 2.2.22 has been modified. The cautions given in Sections 4.2.3 and 4.2.5 have been modified. Table 4-3 has been added. A caution has been added to (2) of Section 5.3. Table 5-2 has been modified. A caution has been added to Section 5.6.2. Timer clock selection register 0 format has been modified. Chapter 6 Chapter 10 Tables 6-2 and 6-6 have been modified. Tables 6-3 and 6-7 have been modified. A caution has been added to (2) of Section 6.3. Cautions have been added to (3) and (4) of Section 6.4.4. Figure 6-32 has been modified. Figure 6-34 has been modified. A caution has been added to timer clock selection register 1 format. Table 7-7 has been added. Timer clock selection register 2 format has been modified. Chapter 8 Chapter 9 Chapter 11 In Section 12.5, "(6) A/D conversion end interrupt request flag (INTAD)" has been changed to "(6) Interrupt request flag (ADIF)." Also, (8) has been deleted. A note has been deleted from Table 13-1. A caution has been added to timer clock selection register 3 format. Serial bus interface control register format has been modified. Figure 13-21 has been modified. Table 14-2 has been modified. (3) has been added to Section 14.4.3. Chapter 14 Chapter 12 Chapter 7 Chapter 6 Chapter 5 Revised Throughout Chapter 1 Chapter 2 Chapter 4 Chapter 13 User's Manual U10105EJ4V1UM00 487 APPENDIX D REVISION HISTORY (4/5) Edition chapter Third Major changes Revised The 1/2 bias method has been modified in the LCD drive power supply connection examples (with on-chip split resistor and with external split resistor). The following LCD drive waveform examples have been modified: Static LCD drive waveform examples 2-time-division LCD drive waveform examples (1/2 bias method) 3-time-division LCD drive waveform examples (1/2 bias method) 3-time-division LCD drive waveform examples (1/3 bias method) 4-time-division LCD drive waveform examples (1/3 bias method) Chapter 16 "Interrupt Functions" has been changed to Chapter 16 "Interrupt and Test Functions". Section 16.5 has been added. A caution relating to be specification of the writing address has been added to Section 19.2. Sections 20.2 and 20.3 have been deleted. Version of PC DOS: 3.1 -> 3.3 to 5.0 The 3.5-inch 2HC floppy disk format has been added to the supported distribution media for the IBM PC/AT. Drawing for conversion adapter (EV-9500GC-100) has been added. The fuzzy inference development support system has been changed. Appendix C of the previous version has been deleted. Appendix C has been newly added. Chapter 15 Chapter 16 Chapter 19 Chapter 20 Appendix A,B Appendix A Appendix B -- Appendix C 488 User's Manual U10105EJ4V1UM00 APPENDIX D REVISION HISTORY (5/5) Edition chapter Fourth Major changes PD78064Y subseries has been added for target devices. * Recommended connections of the following unused pins has been modified. P07/XT1, P110 to P117, VPP * I/O circuit type of the following pins has been modified. P110 to P117 A caution given in Figure 7-4 has been modified and added. A caution given in Figure 7-6 has been modified. Figure 10-1 has been modified. Figure 14-2 has been modified. Section 14.5(7) has been modified and Figure 14-12 has been added. Figure 15-4 has been modified. Figure 15-21 has been modified. Section 15.4.4(c) has been modified. Figure 15-34 has been modified. Figure 17-1 has been modified. Range of baud rate transmit/receive clock generated by main systm clock has been changed. 75 bps to 38400 bps -> 75 bps to 76800 bps Table 20-1 has been modified. Description of operation conditions in HALT mode has been separated to those under main system clock operation and subsystem clock operaion. Cautions given in Section 20.2.2(1) have been modified. Table 20-3 has been modified. Description of operation conditions in STOP mode has been separated to those under main system clock operation and subsystem clock operaion. Description of QTOP microcontroller has been added to Section 22.5. Chapter 22 Chapter 20 Chapter 17 Chapter 15 Chapter 10 Chapter 14 Revised Throughout Chapter 3 Chapter 7 HP9000 series 700 has been added to the host machine for development Appendix A, B tools and embedded software. System simulator (SM78K0) has been added for development tools. Section A.4 has been added. OS(MX78K0) has been added for embedded software. Appendix B Appendix A User's Manual U10105EJ4V1UM00 489 [MEMO] 490 User's Manual U10105EJ4V1UM00 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6465-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: 044-548-7900 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 99.1 Excellent Good Acceptable Poor |
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